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HSPICE Circuit Simulation Interface

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This chapter contains the following topics:

• Overview
• Running HSPICE
• Hierarchical Netlisting

Overview

Using the HSPICE interface is similar to using the SPICE interface. Before reading this chapter, which contains information specific to running an HSPICE simulation, read the chapter on the SPICE interface.

• With the HSPICE interface you can
  • Generate flat or hierarchical netlists
  • Run local and remote simulations
  • Use element and model parameters supported by HSPICE
• HSPICE differs from SPICE in its handling of waveform output from multiple analysis simulation runs.
  The waveforms are written in the Parameter Storage Format (PSF) format if the psf=1 option is set in your control file. The waveforms are stored in the psf directory in the simulation run directory and can be viewed using the Waveform Display program.

Running HSPICE

This section describes the following:

• Creating the schematic
• Generating the run directory
• Editing the control file
• Starting the analysis run
• Generating the netlist
• Creating the input file
• Running the simulation
• Translating the output
• Viewing the results

Most of this information is covered in greater detail in the Virtuoso Schematic Editor L and Simulation Environment Help. Here you will find only what is specific to HSPICE.

Creating the Schematic

Create schematics for HSPICE simulation in the same way as any other schematic in the Virtuoso Studio Design Environment. The main difference is that each cell in the schematic (for example, transistors, resistors, capacitors) must have a symbol and an hspice view to be recognized by the HSPICE interface. For a list of the netlisting properties required for the hspice view, see “Primitive Cell Requirements”.

Generating the Run Directory

The first time you run a simulation, select the Initialize command from the Simulation menu to generate a run directory. This run directory is where the control, netlist, and simulation input and output files are kept for the simulation being run. When you want to keep an older simulation instead of overwriting it, you can generate and use multiple simulation run directories. Refer to Simulation Environment Help.

Editing the Control File

When the system initially creates the run directory, it also creates a dummy control file.

Edit this file to include any information that is not in the schematic. Add the psf option on the .options line in the control file. Set psf=1 or psf=2, which tells HSPICE to generate a waveform file in the binary or ASCII PSF format respectively, as required by the simulation environment. You can also specify just the .option keyword in the control file. To disable the PSF and other options in an hspiceD netlist specify just the .option keyword in the control file.

Edit the hspice.inp file to add stimulus data and edit the hspice.sim file to add simulator commands.

Starting the Analysis Run

With the schematic entered and the control file generated, you are ready to start the simulation. Select the Netlist/Simulate command from the Simulation menu. This command netlists the schematic and starts the simulation; simulation can be run in the background or foreground. Each step in the analysis process is described below.

Generating the Netlist

The simulation environment creates an HSPICE netlist for the desired schematic. This netlist contains the connectivity description in the proper format for HSPICE. See “Formatting Functions” for information about formats. You can generate a flat or a hierarchical netlist. Both have the same information, but their formats are different. You control the type of netlist generated by setting the simNetlistHier simulation environment variable. If this variable is set to t, a hierarchical netlist is created; otherwise, a flat netlist is created by default. Typically, you set this variable in your .simrc file.

Note the following:

• By default, parameter values are converted to engineering notation in HSPICE netlist. For example, the parameter w=100u is written as W=100e-6 in the netlist. Set the setEngNotation environment variable to in your .cdsenv file to print the parameter values as is (without conversion to engineering notation) in the netlist.
  

  hspiceD.envOpts setEngNotation boolean nil

  To revert to the default behavior, set the variable to t. For example:

  hspiceD.envOpts setEngNotation boolean t

• For devices other than diodes and MOS transistors, the netlister netlists only a predefined list of parameters. If you add user defined parameters in the CDF Simulation Information (simInfo) of devices other than diodes and MOS transistors, those parameters will not be netlisted. For such devices, you can write a custom netlist procedure to netlist user defined parameters.

Creating the Input File

Once the netlist is generated, the HSPICE interface automatically translates the instance and net names in the control, hspice.inp, hspice.sim, and netlist files to legal names for HSPICE. When the translation completes, these files are assembled to create the HSPICE si.inp input file.

Running the Simulation

When the simulator input file (si.inp) is created, simulation starts. If the simHost variable is set to a different machine, the simulation runs remotely.

For more information about remote simulation, refer to Simulation Environment Help.

Translating the Output

When the simulation is finished, the simulation interface translates net and instance names that were previously translated back to the original user-assigned names. The resulting translated text output is stored in the si.out file.

Viewing the Results

The simulation environment notifies you when analysis is complete so you can view the outputs. Information about the simulation run is recorded in the si.log file when a background simulation is run.

Hierarchical Netlisting

The hierarchical netlister produces a netlist that is easier to read and understand than one that has been flattened. For more information about flat netlisting, refer to Simulation Environment Help. The following are primary features of a hierarchical netlist:

• The hierarchy of the netlist duplicates the hierarchy of your design. The netlister creates a separate subcircuit for each cell in your schematic. This can dramatically reduce the number of lines in the netlist, since the subcircuit definition is printed only once and all instances of the cell are netlisted as calls to the subcircuit.
• Unlike the flat netlister, which translates every instance and net name to a unique name, the hierarchical netlister translates only names that are illegal to HSPICE. To avoid naming conflicts, the hierarchical netlister makes every effort to keep the original user-assigned names in the netlist. When necessary, names are mapped, but the mapping is minimal. Characters that are illegal in HSPICE names are
  . , ( ) [ ] $ ’ < >
  When any of these characters is found in a name, the character is automatically deleted. In some cases, the name is completely remapped. Usually this occurs when you have specified a name that is too long. HSPICE names are limited to eight characters. If a name is longer than eight characters, it is mapped by the interface.
  When HSPICE maps the entire name, it assigns a unique number preceded by an n for net names, an i for instance names, and an m for macro and model names.
  The first character of an element name in the netlist indicates the element type. The netlister automatically adds a prefix to all instance names. For example, MOSFET instance names are prefixed with m, and resistor names with r.

Primitive Cell Requirements

A cell must have both a symbol and an hspice view to be recognized by the HSPICE interface. The hspice view for a cell must contain the same pins that exist in the symbol view for the cell. For netlisting, define the following properties in the hspice view:

• NLPElementPostamble
  Indicates to the flat netlister how to format the element cards for an instance of the cell.
• NLPModelPreamble
  Indicates to the flat netlister how to format the model card for an instance of the cell.
• hnlHspiceFormatInst
  Indicates to the hierarchical netlister what procedure to call to format and print the element cards for an instance of the cell.
• hnlHspiceParamList
  Indicates to the hierarchical netlister what parameters can be inherited. The value of this parameter must be the name of a Cadence SKILL™ language variable, whose value is the list of parameters that can be inherited. Any parameter that does not appear on this list cannot inherit its value and must be assigned fixed values.
• hnlHspiceFormatModel
  Indicates to the hierarchical netlister what procedure to call to format and print the model card for an instance of the cell.

Example

The following are the property values for the above netlisting properties in the hspice view of the nmos cell in the sample library:

NLPElementPostamble = nlpExpr("[@NLPElementComment:%\n]
    [@NLPnmosElementCard]")
NLPModelPreamble = nlpExpr("[@NLPmosfetModelCard]")
hnlHspiceFormatInst = "hnlHspicePrintNMOSfetElement()"
hnlHspiceParamList = "hnlHspiceMOSfetParamList"
hnlHspiceFormatModel = "hnlHspicePrintMOSfetModel()" 

The flat netlister uses expressions defined in the nlpglobals cell to format elements and models. The first two properties, therefore, tell the netlister to format the element and model cards with the NLPnmosElementCard and NLPmosfetModelCard expressions, defined in the hspice view of the nlpglobals cell.

For hierarchical netlisting, the element and model cards are formatted using the procedures defined in the hspice formater. For the nmos transistor, these procedures are called hnlHspicePrintNMOSfetElement and hnlHspicePrintMOSfetModel.

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