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Verilog Netlister Functions
This topic describes the SKILL APIs of tools used to netlist and simulate digital designs in the Virtuoso® design environment. It provides information on the SKILL functions that you can use with the following Virtuoso applications:
- Virtuoso Verilog Environment for NC-Verilog Integration
- Virtuoso Verilog Environment for SystemVerilog Integration
- Virtuoso Open Simulation System
- Virtuoso VHDL Toolbox
This topic is aimed at designers of integrated circuits and assumes that you are familiar with:
- The Virtuoso Studio design environment and application infrastructure mechanisms designed to support consistent operations between all Cadence tools.
- The applications used to design and develop integrated circuits in the Virtuoso Studio design environment, notably Virtuoso Layout Suite and Virtuoso Schematic Editor.
- The design and use of parameterized cells.
- Component Description Format (CDF), which lets you create and describe your own components for use with ADE.
- Cadence SKILL™ language.
This topic lists the Cadence® SKILL functions associated with the Verilog netlister for invoking the form and update cellviews.
Only the functions listed below are supported for public use. All other functions, regardless of their name or prefix, and undocumented aspects of the functions described below, are private and are subject to change at any time.
Licensing Requirements
For information on licensing in the Virtuoso Studio design environment, see the Virtuoso Software Licensing and Configuration User Guide.
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