6
Customizing the HNL Net-Based Netlister
In addition to instance-based netlisting capability, HNL supports net-based netlisting to facilitate the interface to net-based simulators and tools.
Similar to the instance-based capability, HNL traverses a given design, retrieves the relevant information, and sets up the environment for a formatter to generate the required netlist. Most processes are performed automatically by HNL, but generating a netlist in the targeted syntax is performed by the formatter.
The design of the formatter is similar to an instance-based one. When designing a net-based netlist formatter, the designer MUST set the HNL variable hnlInstBased to nil, which signals that the net-based capability is desired.
Flow of Net-Based HNL
When running in the net-based mode, HNL first traverses all models (cells) in the given design, identifying all global signals while preparing for the netlist generation steps. The design traversal and global signals identification processes are identical for both net-based and instance-based HNL, but are different from the incremental HNL. The net-based traversal cannot be used with the hierarchical netlister in incremental mode.
After the initial design traversal, HNL prints the required netlist header as instructed, then goes through all referred models in the design for netlist generation, beginning with call hnlPrintNetlistHeader(), then going through call hnlDoNetBased() and call hnlPrintNetlistFooter().
The hnlPrintNetlistHeader() and hnlPrintNetlistFooter() procedures are explained in the HNL chapter of this manual. The hnlDoNetBased() procedure addresses each cell, prepares the internal data structures, and calls the procedures specified by the HNL variable, hnlTopCellNetFuncs, if the cell being netlisted is the top design cellview, or hnlMacroCellNetFuncs otherwise.
By default, hnlTopCellNetFuncs will activate the procedures hnlPrintTopCellHeader, hnlPrintSignal, and hnlPrintTopCellFooter while hnlMacroCellNetFuncs activates hnlPrintDeviceHeader, hnlPrintPorts, hnlPrintSignal, and hnlPrintDeviceFooter. The hnlPrintSignal procedure is responsible for netlisting each signal and its connection while the procedures with the name “Header” are responsible for netlisting the header of a cellview and netlist that are to appear before the signals and their connections. Similarly, “Footer” procedures are for netlisting all netlists that are to appear after the connections and the footer.
The default procedure, hnlPrintSignal, goes through all signals in hnlCurrentCell, finds the connectivity to the signal, then assigns the proper values to the supported variables for netlist formatting. For each signal, the procedures hnlPrintSignalHeader, hnlPrintInst, and hnlPrintSignalFooter are called to generate the netlist.
For descriptions of the above-mentioned procedures, refer to the “HNL Procedures for Net-Based Netlisting” section in this chapter.
The default flow of hnlPrintSignal is
for each signal in the cell being netlisted
callhnlPrintSignalHeader( )
for each instance connect to current signal
prepare variables for netlisting
callhnlPrintInst( )endfor
callhnlPrintSignalFooter( )endfor
For details on the variables available for the netlist formatter, refer to the “HNL Variables for Net-Based Netlisting” section in this chapter.
HNL Variables for Net-Based Netlisting
The following HNL variables are available for use by the formatter for net-based netlisting. Some of these variables can be redefined by the user, and some are only defined during the evaluation of certain functions.
All variables used for managing the name mapping function are the same as for instance-based HNL. All variables used for performing output formatting are also identical to instance-based HNL. All names provided by HNL for performing net-based netlisting are single bit names, which means that signal names are always used instead of net names, and the name of each iteration of an instance is used for iterated instances.
hnlInstBased
The default is t. You must set the hnlInstBased variable to nil to run HNL in net-based mode.
hnlListOfAllCells
The list of all cellviews used in the given design. Defined after the initial design traversal is completed.
hnlListOfAllStoppingCells
The list of all primitives (stopping cellviews) used in the given design. Defined after the initial design traversal is completed.
hnlCurrentCell
The dbCellViewId of the current cell being netlisted. Defined by hnlDoNetBased().
hnlAllTerms
The list of all terminals in hnlCurrentCell. Defined by hnlDoNetBased().
hnlAllTermNames
The list of the names of all of the bits of all of the terminals in hnlCurrentCell. The names in this list are flattened (reduced to single bit names) and stored in the same order as hnlAllTerms. Defined by hnlDoNetBased().
hnlCellAllTermNames
Contains the terminal names of the current cell in the same order as that of the nets connected to them in the SKILL variable hnlCellNetsOnTerms. It is populated only when either of the two SKILL variables, hnlProcessDifferentPmAndInstTerminalRepresentation or hnlProcessConnectionsInAscendingOrder, is set to t. If neither of these two variables is set, hnlCellAllTermNames is set to nil.
hnlCellInTerms
The list of all input terminals in hnlCurrentCell. Defined by hnlDoNetBased().
Inherited terminals can be found in this list but since these are real terminals there are db id. associated with them. Here for inherited terminals the relationship with the entries in hnlCellInputs are db id. to netlister-generated names. These netlister-generated names are the same ones that appeared in hnlCellInputs.
For module buffer, the value is list( db_id_IN ).
hnlCellInTermName
The list of the names of all the bits of all input terminals in hnlCurrentCell. They are flattened and stored in the same order as hnlCellInTerms. Defined by hnlDoNetBased().
hnlCellOutTerms
The list of all output terminals in hnlCurrentCell. Defined by hnlDoNetBased().
Inherited terminals can be found in this list but since these are real terminals there are db id. associated with them. Here for inherited terminals the relationship with the entries in hnlCellOutputs are db id. to netlister-generated names. These netlister-generated names are the same ones that appeared in hnlCellInputs.
For module buffer, the value is list( db_id_OUT ).
hnlCellOutTermNames
The list of the names of all the bits of the output terminals in hnlCurrentCell. They are flattened and stored in the same order as hnlCellOutTerms. Defined by hnlDoNetBased().
hnlCellOtherTerms
The list of all terminals in hnlCurrentCell that are neither input nor output terminals. Defined by hnlDoNetBased().
Logically there is no db id. for pseudo port created as a result of inherited signal. A netlister-generated-name generated by HNL is used as a place-holder instead. Inherited terminals can be found in this list but since these are real terminals there are db id. associated with them. Here for inherited terminals the relationship with the entries in hnlCellOutputs are db id. to netlister-generated names. These netlister-generated names are the same ones that appeared in hnlCellOthers.
For module buffer, there are no db ids for the pseudo ports created but pseudo-names generated by HNL are used as the place holders for the inherited connections. The value is list( “inh_gnd” “inh_vdd”)
hnlCellOtherTermNames
The list of the names of all the bits of the terminals in hnlCurrentCell that are neither input nor output terminals. They are flattened and stored in the same order as hnlCellOtherTerms.
hnlTopCell
The dbCellViewId of the top cellview of the design being netlisted. This variable is defined throughout the netlisting process, but is invalidated after netlisting is completed because the top cell is automatically closed by HNL.
hnlTopCellNetFuncs
A variable defining the procedures to be called by hnlDoNetBased for netlisting the top cellview. The default value is
'( "hnlPrintTopCellHeader( )"
"hnlPrintSignal( )"
"hnlPrintTopCellFooter( )"
)
hnlCurrentSignal
The signal in hnlCurrentCell that is being netlisted. Defined in hnlPrintSignal(). It becomes invalid after all signals in hnlCurrentCell have been netlisted.
hnlCurrentSignalTerms
The names of the terminals in hnlCurrentCell that are connected to the bits of the hnlCurrentSignal. Defined in hnlPrintSignal().
hnlCurrentSignalName
Name of hnlCurrentSignal. Defined in hnlPrintSignal().
hnlCurrentInst
The instance in hnlCurrentCell which has one of its pins connected to hnlCurrentSignal. This variable may refer to an iterated instance. The variable hnlCurrentInst should be used in conjunction with the variable hnlCurrentIteration to identify the instance being netlisted. Defined by hnlPrintSignal() after hnlPrintSignalHeader() has been called.
hnlCurrentInstName
The name of the iteration of the instance that is currently being netlisted as defined by hnlCurrentInst and hnlCurrentIteration. Defined in hnlPrintSignal().
hnlCurrentIteration
The iteration number of the instance of hnlCurrentInst which is being netlisted. Defined in hnlPrintSignal().
hnlCurrentType
The cell name of the master of hnlCurrentInst. Defined in hnlPrintSignal().
hnlCurrentMaster
The dbCellViewId of the view switched master of hnlCurrentInst. Defined by hnlPrintSignal(). It is valid only during evaluation of the hnlPrintInst() function.
hnlCurrentInstPort
The instance terminal of hnlCurrentInst which is connected to hnlCurrentSignal. This variable may refer to a multiple bit terminal in order to access the terminal bit that is connected. hnlCurrentInstPortIndex should be used when needed. Defined by hnlPrintSignal(). Valid only during evaluation of the hnlPrintInst() function.
hnlCurrentPortName
The name of hnlCurrentInstPort. Defined by hnlPrintSignal(). To get the name of the terminal bit that is connected to hnlCurrentSignal, you must use dbGetMemName(hnlCurrentInstPortName hnlCurrentInstPortIndex).
hnlCurrentInstPortIndex
The index of the bit of hnlCurrentInstPort that is connected to the current signal. Defined by hnlPrintSignal().
hnlInstMasterPort
The terminal on hnlCurrentMaster that is connected to the current signal. Defined by hnlPrintSignal().
hnlMacroCellNetFuncs
A variable defining the procedure to be called by hnlDoNetBased for netlisting all cells that are not the top cell. The default value is
'( "hnlPrintDeviceHeader( )"
"hnlPrintPorts"
"hnlPrintSignal( )"
"hnlPrintDeviceFooter( )"
)
hnlProcessAliasSignalWithSourceDirection
A variable that specifies that the netlister uses aliasing between more than two signals. By default, it is set to nil. It requires adding the direction property of the net, where the property value must be set to the source.
The following example shows aliasing between the signals a, z<0>, and z<1>.

Here, if the source net is a, then the direction property must be set on net a, where the property value is set to source.
hnlProcessConnectionsInAscendingOrder
Specifies that pins should be printed in ascending order during netlisting. By default, it is set to nil.
HNL Procedures for Net-Based Netlisting
Various HNL SKILL functions are available for use by the formatter for net-based netlisting. For details, see OSS Functions in the Digital Design Netlisting and Simulation SKILL Reference.
Other Variables and Procedures
In addition to the variables and procedures previously described, other variables and procedures are available, as categorized below:
Controlling the Format of the Netlist File
If you call hnlPrintString() to output the netlist, you should set the following variables.
hnlMaxLineLength
hnlCommentStr
hnlDriverWillPrint
hnlLinePostfix
hnlLinePrefix
Variable and Name Mapping Functions
The same set of name mapping procedures are supported for net-based netlisting as for instance based netlisting. All the related variables should be set by the formatter accordingly. Following are the variables you should set.
hnlMapIfFirstChar
hnlMapIfInName
hnlMapInstFirstChar
hnlMapInstInName
hnlMapModelFirstChar
hnlMapModelInName
hnlMapNetFirstChar
hnlMapInNetName
hnlMaxNameLength
hnlNamePrefix
hnlMapTermFirstChar
hnlMapTermInName
simNetNamePrefix
simInstNamePrefix
simModeNamePrefix
Following are the available name mapping functions.
hnlMapInstName
hnlMapModelName
hnlMapNetName
hnlMapName
Other Procedures and Functions
All procedures and functions supported for instance-based netlisting are also supported for net-based netlisting, unless redefined in the “HNL Procedures for Net-Based Netlisting” section. For details on these procedures and functions, refer to the “Customizing the Hierarchical Netlister” chapter in this manual.
Other Variables
All variables supported in instance-based HNL are also supported for net-based netlisting, unless redefined in the “HNL Variables for Net-Based Netlisting” section.
Procedures the Formatter Must Define
The following procedures must be included when you define the formatter.
hnlPrintTopCellHeader( )
The procedure called before calling hnlPrintSignal() for netlisting the top-level cell. All the variables set up by hnlDoNetBased() are available.
hnlPrintTopCellFooter( )
The procedure called after hnlPrintSignal() is completed for the top cell. This is the last procedure called for netlisting the top cell.
hnlPrintDeviceHeader( )
The procedure called before calling hnlPrintSignal() for all but the top-level cellview. All the variables set up by hnlDoNetBased() are available. This procedure calls for netlisting information that is not managed/netlisted by hnlPrintSignal().
hnlPrintDeviceFooter( )
The procedure called after hnlPrintSignal() is completed for all but the top-level cellview. This procedure is called to generate a netlist after all signals’ connectivities that are not handled by hnlPrintSignal(). Default is nil procedure.
hnlPrintPorts( )
The procedure to netlist the port definition for each cellview.
hnlPrintSignalHeader( )
The procedure to netlist the signal definition before it is netlisted. Called by hnlPrintSignal before hnlPrintInst(), which is before all instances connected to hnlCurrentSignal have been netlisted.
hnlPrintSignalFooter( )
The procedure to netlist the signal definition after it is netlisted. Called by hnlPrintSignal after hnlPrintInst(), which is after all instances connected to hnlCurrentSignal have been netlisted.
hnlPrintInst( )
The procedure to netlist an instance (defined by hnlCurrentInst and hnlCurrentIteration) and its connectivity to signal hnlCurrentSignal. All variables described in the previous section are available and assigned the proper values when this procedure is called. This procedure MUST be defined by all formatters.
Designing an HNL Net-Based Formatter
Designing a formatter for net-based syntax is similar to designing a formatter for instance-based syntax. Most of the required data is available, and the environment is ready to be used. Simply follow the procedure below to complete designing and coding of your formatter.
Determine Name Mapping and Netlist Syntax Needed
Determine the netlist and name mapping requirements needed to generate the correct netlist.
Initialize Variables
You must set hnlInstBased to nil. Do not forget to set the hnl variables that control name mapping and output formatting to the desired values. If you want to set values for other HNL variables, refer to the “Customizing the Hierarchical Netlister” chapter in this manual.
Code the Needed Procedures
Design the procedures for your formatter by following the procedure in the “Controlling the Format of the Netlist File” section. Then, code the following routines accordingly: hnlPrintInst(), hnlPrintTopCellHeader(), hnlPrintTopCellFooter(), hnlPrintSignalHeader(), hnlPrintSignalFooter(), hnlPrintPorts(), hnlPrintDeviceHeader(), and hnlPrintDeviceFooter(). You may need to code some additional procedures to help handle some specific formatter needs.
Net-Based Netlister Design Example
This section includes a simple net-based netlister design to demonstrate the fundamentals of designing a similar netlist formatter using the variables and procedures previously discussed.
For this example, the syntax of the target netlist complies with the following form:
Model modelName;
Ports
[PortNames [=signalName] ;]*
endPorts
Object
[InstanceName InstanceType ;]*
endObjects
Connection
[signalName [InstanceName.pinName]* ;]*
endConnection
endModel [modelName].
where [ ] specifies optional field, [ ]+ specifies a field that must appear at least once, and [ ]* specifies a field that may occur any number of times. This syntax applies to all modules of a design, except that the keyword Design is to be used in place of Model for the top-level modules.
Designing the Netlister
For this example, the legal syntax for a name is a string that starts with an alphabet and does not contain any of the following: “.” “,” “+” “-” “*” “@” “%” “#” and “!”. All comment lines are preceded by “#”. It is also assumed that “.” is used by the target simulator as hierarchy delimiter.
All module names are mapped using hnlMapModelName(), all signal (net) names are mapped using hnlMapNetName(), all port names are mapped using hnlMapped Name(), and all instance names are mapped by hnlMapInstName(). The port names are derived directly from the terminal names. Pin names of instances are the port names of its master cellview.
The Formatter
The netlist formatter is designed as shown below.
;
; This example shows how to use HNL to design a net-based netlist formatter.
;
; First, define the need variable for net-based netlisting.
hnlInstBased = nil
hnlFormatFuncsLoaded = t
hnlNetlistFileName = "netlist"
hnlSetDef( ’hnlMaxNameLength 12 )
hnlSetDef( ’hnlHierarchyDelimeter "." )
hnlSetDef( ’hnlMaxLineLength 72 )
hnlSetDef( ’hnlMapTermFirstChar list( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9"
"." "," "+" "-" "*" "%" "@" "#" "!"
)
)
hnlSetDef( ’hnlMapTermInName list( "." "," "+" "-" "*" "#" "!" "@" "<" ">" )
)
hnlSetDef( ’hnlMapNetFirstChar list( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9"
"." "," "+" "-" "*" "%" "@" "#" "!"
)
)
hnlSetDef( ’hnlMapNetInName list( "." "," "+" "-" "*" "#" "!" "@" "<" ">" )
)
hnlSetDef( ’hnlMapInstFirstChar list( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9"
"." "," "+" "-" "*" "%" "@" "#" "!"
)
)
hnlSetDef( ’hnlMapInstInName list( "." "," "+" "-" "*" "#" "!" "@" "<" ">" )
)
hnlSetDef( ’hnlMapModelFirstChar list( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9"
"." "," "+" "-" "*" "%" "@" "#" "!"
)
)
hnlSetDef( ’hnlMapModelInName list( "." "," "+" "-" "*" "#" "!" "@" "<" ">" )
)
hnlSetDef( ’hnlFormaterUnbindFuncs ’( hnlSetOutPutVars hnlPrintNetlistHeader hnlPrintNetlistFooter
hnlPrintTopCellHeader hnlPrintTopCellFooter
hnlPrintDeviceHeader hnlPrintDeviceFooter
hnlPrintPorts hnlPrintInst
hnlPrintSignalHeader hnlPrintSignalFooter
hnlPrintMyPort hnlListMyObject
)
)
;
; Set the variables which control name mapping and output.
;
hnlIfNoProcedure( hnlSetOutputVars()
prog( ()
hnlNamePrefix = "hnl"
simNetNamePrefix = "N"
simModelNamePrefix = "M"
simTermNamePrefix = "T"
simInstNamePrefix = "I"
simLinePrefix = "+"
simCommentStr = "#"
hnlDriverWillPrint = t
return( t )
)
)
;
; Print one line of comment at the begining of netlist.
;
hnlIfNoProcedure( hnlPrintNetlistHeader()
let( ( buffer )
sprintf( buffer "#\n#Netlist for design %s.\n#\n" hnlTopCell ~> cellName )
hnlPrintString( buffer )
)
)
;
; Print one line of comment at the end of netlist.
;
hnlIfNoProcedure( hnlPrintNetlistFooter()
hnlPrintString( "#\n#End of Netlist.\n#\n" )
)
;
; Because the IO port definition is taken care off elsewhere, do
; nothing.
;
hnlIfNoProcedure( hnlPrintPorts()
t
)
;
; Print the top cell definition for the generated netlist.
;
hnlIfNoProcedure( hnlPrintTopCellHeader()
let( ( buffer )
sprintf( buffer "#\n# Netist for top level Cell.\n#"
hnlPrintString( buffer )
if( hnlMultipleCells( hnlCurrentCell ~> cellName ) then
sprintf( buffer "Design %s ;\n" hnlMapModelName( hnlCurrentCell ∼>
fileName ))
else
sprintf( buffer "Design %s ;\n" hnlMapModelName( hnlCurrentCell ∼>
cellName ))
)
hnlPrintString( buffer )
hnlPrintMyPorts()
hnlMyListObjects()
)
)
;
; Print the cell definition closure for the top cell.
;
hnlIfNoProcedure( hnlPrintTopCellFooter()
let( ( buffer )
if( hnlMultipleCells( hnlCurrentCell ~> cellName ) then
sprintf( buffer "endDesign %s.\n" hnlMapModelName( hnlCurrentCell ∼>
fileName ))
else
sprintf( buffer "endDesign %s.\n" hnlMapModelName( hnlCurrentCell ∼>
cellName ))
)
hnlPrintString( buffer )
)
)
;
; Print the netlisting definition for a macro cell.
;
hnlIfNoProcedure( hnlPrintDeviceHeader()
let( ( buffer )
sprintf( buffer "#\n# Netist for macro Cell.\n#" )
hnlPrintString( buffer )
if( hnlMultipleCells( hnlCurrentCell ~> cellName ) then
sprintf( buffer "Design %s ;\n" hnlMapModelName
( hnlCurrentCell ∼>
fileName ))
else
sprintf( buffer "Design %s ;\n" hnlMapModelName
( hnlCurrentCell ∼>
cellName ))
)
hnlPrintString( buffer )
hnlPrintMyPorts()
hnlMyListObjects()
)
)
; ; Print the netlist definiton closeure for a macro cell.
;
hnlIfNoProcedure( hnlPrintDeviceFooter() let( ( buffer )
if( hnlMultipleCells( hnlCurrentCell ~> cellName ) then
sprintf( buffer "endModel %s.\n" hnlMapModelName
( hnlCurrentCell ∼>
fileName ))
else
sprintf( buffer "endModel %s.\n" hnlMapModelName
( hnlCurrentCell ∼>
cellName ))
)
hnlPrintString( buffer )
)
)
;
; Print IO port definition.
;
hnlIfNoProcedure( hnlPrintMyPorts()
let( ( term termNames thisName count bit buffer signal )
hnlPrintString( "Ports\n" )
termNames = hnlAllTermNames
foreach( term hnlAllTerms
count = term ∼> width - 1
for( bit 0 count
thisName = car( termNames )
termNames = cdr( termNames )
hnlPrintString( hnlMapTermName( thisName ) )
if( ( signal = dbGetMemNetSigName( term ~>
net bit ) ) == nil
then hnlPrintString( "= NC ;\n" )
else
sprintf( buffer "= %s ;\n" hnlMapNetName( signal ) )
hnlPrintString( buffer )
)
)
)
hnlPrintString( "endPorts\n" )
)
)
;
; Print the instance type definition.
;
hnlIfNoProcedure( hnlMyListObjects()
let( ( buffr inst allInst allMaster master temp count num cellName )
hnlPrintString( "Objects\n" )
allInst = hnlFindAllInstInCell( hnlCurrentCell )
allMaster = hnlGetMasterCells( allInst )
temp = allMaster
foreach( inst allInst
master = car( temp )
temp = cdr( temp )
if( hnlMultipleCells( master ~> cellName ) then
cellName = hnlMapModelName( master ~> fileName )
else
cellName = hnlMapModelName( master ~> cellName )
)
count = inst ∼> numInst - 1
for( num 0 count
sprintf( buffer "%s %s ;\n" hnlMapInstName(
dbGetMemName( inst ~> name num ) ) cellName )
hnlPrintString( buffer )
)
)
hnlPrintString( "endObjects\n" )
)
)
;
; Print the signal definition.
;
hnlIfNoProcedure( hnlPrintSignalHeader()
let( ( buffer )
sprintf( buffer "# Signal %s.\n" hnlCurrentSignalName )
hnlPrintString( buffer )
hnlPrintString( hnlMapNetName( hnlCurrentSignalName ) )
)
)
;
; Print the definition closure for a signal.
;
hnlIfNoProcedure( hnlPrintSignalFooter()
hnlPrintString( ";\n" )
)
;
; For each inst-terminal connected to hnlCurrentSig, print the
; the connectivity in the desired format.
;
hnlIfNoProcedure( hnlPrintInst()
let( ( buffer )
sprintf( buffer " %s.%s" hnlMapInstName( hnlCurrentInstName )
hnlMapTermName( hnlCurrentInstPortName ) )
hnlPrintString( buffer )
)
)
Sample Output from Formatter Design
The following is sample output from the formatter design example shown in the previous section.
#
#Netlist for design design.
#
#
# Netist for macro Cell.
#Design test1 ;
Ports
I0= I0 ;
I1= I1 ;
T0= N1 ;
T2= N3 ;
O= O ;
endPorts
Objects
I1 or2 ;
I0 or2 ;
I2 xor2 ;
endObjects
# Signal I1.Y.
N4 I1.Y I2.B;
# Signal D<0>.
N1 I1.A;
# Signal I0.Y.
N5 I0.Y I2.A;
# Signal I1.
I1 I0.B;
# Signal I0.
I0 I0.A;
# Signal D<1>.
N3 I1.B;
# Signal O.
O I2.Y;
endModel test1.
#
# Netist for macro Cell.
#Design test2 ;
Ports
T6= N7 ;
T8= N9 ;
T0= N1 ;
T2= N3 ;
OUT= OUT ;
endPorts
Objects
I0 test1 ;
endObjects
# Signal D<0>.
N1 I0.T0;
# Signal I<0>.
N7 I0.I0;
# Signal D<1>.
N3 I0.T2;
# Signal OUT.
OUT I0.O;
# Signal I<1>.
N9 I0.I1;
endModel test2.
#
# Netist for macro Cell.
#Design test ;
Ports
O1= O1 ;
I1= I1 ;
I2= I2 ;
I3= I3 ;
I0= I0 ;
endPorts
Objects
I4 and2 ;
I5 and2 ;
I0 xor2 ;
endObjects
# Signal I4.Y.
N10 I4.Y I0.A;
# Signal O1.
O1 I0.Y;
# Signal I3.
I3 I5.B;
# Signal I2.
I2 I5.A;
# Signal I1.
I1 I4.B;
# Signal I0.
I0 I4.A;
# Signal I5.Y.
N11 I5.Y I0.B;
endModel test.
#
# Netist for top level Cell.
#Design design ;
Ports
T12= N13 ;
T14= N15 ;
T= T ;
N= N ;
P= P ;
D= D ;
M= M ;
J= J ;
JUNK= JUNK ;
T16= N17 ;
T18= N19 ;
T20= N21 ;
T22= N23 ;
T24= N25 ;
T26= N27 ;
T28= N29 ;
T30= N31 ;
endPorts
Objects
I2 or2 ;
R10 res ;
I11 buffer ;
I12 inv ;
I15 cmos ;
N19 nmos ;
P20 pmos ;
I3 and2 ;
I0 test ;
I32 test2 ;
I1 test1 ;
endObjects
# Signal A<3>.
N23 I1.I0 I0.I3;
# Signal D.
D I15.D N19.D;
# Signal R10.Y.
N32 R10.Y I12.A;
# Signal A<1>.
N19 I1.T0 I0.I1;
# Signal N19.S.
N33 P20.D N19.S;
# Signal DATA<2>.
N29 I32.T0;
# Signal I0.O1.
N34 I0.O1 I3.A I2.A;
# Signal IN<3>.
N25 I32.T6;
# Signal R<1>.
N15 I3.Y;
# Signal I1.O.
N35 I1.O I3.B I2.B;
# Signal A<2>.
N21 I1.I1 I0.I2;
# Signal T.
T I12.Y;
# Signal I11.Y.
N36 I11.Y R10.A;
# Signal JUNK.
JUNK I32.OUT;
# Signal A<0>.
N17 I1.T2 I0.I0;
# Signal P.
P I15.GP;
# Signal N.
N I15.GN N19.G;
# Signal DATA<3>.
N31 I32.T2;
# Signal M.
M P20.S;
# Signal J.
J P20.G I15.S I11.A;
# Signal IN<4>.
N27 I32.T8;
# Signal R<2>.
N13 I2.Y;
endDesign design.
#
#End of Netlist.
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