lxHierUpdateComponentsAndNets

lxHierUpdateComponentsAndNets(
d_layCellViewID
[ ?initCreatePins { t | nil } ]
[ ?initGlobalNetPins { t | nil } ]
[ ?initCreatePadPins { t | nil } ]
[ ?initCreateInstances { t | nil } ]
[ ?initCreateBoundary { t | nil } ]
[ ?initCreateSnapBoundary { t | nil } ]
[ ?initDoStacking { t | nil } ]
[ ?initDoFolding { t | nil } ]
[ ?initCreateMTM { t | nil } ]
[ ?deleteUnmatchedInsts { t | nil } ]
[ ?deleteUnmatchedPins { t | nil } ]
[ ?updateReplacesMasters { t | nil } ]
[ ?updateWithMarkers { t | nil } ]
[ ?updateLayoutParameters { t | nil } ]
[ ?updateNetSigType { t | nil } ]
[ ?updateNetMinMaxVoltage { t | nil } ]
[ ?updateNetsOnly { t | nil } ]
[ ?virtualHierarchy { t | nil } ]
[ ?skipLeafs { t | nil } ]
[ ?extractSchematic { t | nil } ]
)
=> t / nil

Description

Updates the components and nets for all unique layout masters in the specified layout cellview hierarchy. The layouts are automatically opened in edit mode for update. If a log file name is specified for the hierSummaryLogFileName environment variable, the SKILL function prints the summary information to the specified log file, in addition to printing the information to the default Virtuoso log file.

Arguments

d_layCellViewID
	Database ID of the target layout cellview.
`?initCreatePins`
	Generates all the pins specified in the I/O Pins tab of the Update Components and Nets form. The default is `t`.
`?initGlobalNetPins`
	Generates layout pins for the global nets in the schematic, if the Create option on the I/O Pins tab is selected. If the Create option is not selected, no global pins are created. The default is `t`.
`?initCreatePadPins`
	Generates layout pad pins corresponding to the schematic pins that are connected to the I/O pads, if the Create option on the I/O Pins tab is selected. If the Create option is not selected, no pad pins are created. The default is `t`.
`?initCreateInstances`
	Generates all the instances in the schematic that do not have one of the ignore properties attached to them. The default is `t`.
`?initCreateBoundary`
	Generates a design boundary using the layer and size information specified in the Boundary tab of the Update Components and Nets form. The default is `t`.
`?initCreateSnapBoundary`
	Generates a snap boundary. The default is `nil`.
`?initDoStacking`
	Enables the abutment of ordered lists of MOS transistors into chains when they are generated in the layout. The default is `nil`.
`?initDoFolding`
	Folds transistors into separate fingers to prevent the gate width from exceeding the manufacturing foundry specification size. The default is `nil`.
`?initCreateMTM`
	Preserves user-defined one-to-one, many-to-many, many-to-one, and one-to-many device correspondence defined in the Define Device Correspondence form. User-defined internal bindings made using the Update Binding form are not preserved, and no report is generated for missing devices or shapes within a mapped group. The default is `nil`.
`?deleteUnmatchedInsts`
	Deletes layout instances that no longer exist in the schematic. If `?deleteUnmatchedInsts` is set to `nil`, the unmatched instances are not deleted, but they are represented by a marker in the layout. The default is `nil`.
`?deleteUnmatchedPins`
	Deletes layout pins that no longer exist in the schematic. If `?deleteUnmatchedPins` is set to `nil`, the unmatched pins are not deleted, but they are represented by a marker in the layout. The default is `nil`.
`?updateReplacesMasters`
	Updates existing instances that use an incorrect master to use the correct master. The default is `t`.
`?updateWithMarkers`
	Puts a marker on the instance with the incorrect master and creates a new instance with the correct master, if `?updateReplacesMasters` is set to `t.` If `?updateReplacesMasters` is set to `nil`, the instance with the incorrect master is removed and replaced at the same location with an instance with the correct master. The default is `nil`.
`?updateLayoutParameters`
	Updates the parameters and parameter values on layout instances to match those on their schematic counterparts. The default is `nil`.
`?updateNetSigType`
	Updates the layout net signal types to match their schematic counterparts. The default is `t`.
?UpdateNetMinMaxVoltage
	Updates the minimum and maximum voltages on layout nets to match their schematic counterparts. The default is `t`.
`?updateNetsOnly`
	Updates nets and renames instance mismatches. This argument overrides all the other optional arguments. The default is `nil`.
`?virtualHierarchy`
	Generates virtual hierarchy for schematic symbols that do not have any corresponding layouts. The default value is `nil`.
`?skipLeafs`
	During an update, skips hierarchical layouts that have no instances. The default is `nil`.
`?extractSchematic`
	Extracts the schematic design, if required, before updating the components and nets. The default is `t`. If set to `nil`, the schematic is not extracted and the components and nets are not updated.

Value Returned

`t`	The command was successful.
`nil`	The command was unsuccessful.

Examples

layCV=dbOpenCellViewByType( layLibName layCellName layViewName )

lxHierUpdateComponentsAndNets(layCV)

Uses the default options for performing an update of the components and nets. The schematic is determined from the current connectivity reference, which can be set using the SKILL function lxSetConnRef.

lxHierUpdateComponentsAndNets(layCV ?netsOnly t)

Only updates the nets and instance names mismatches.

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Virtuoso Layout Suite SKILL ReferenceProduct Version IC23.1, November 2023