Dynamic Setup and Hold Check (dyn_setuphold)

Spectre Syntax

title dyn_setuphold node=[node] ref_node=[node] setup_time=<value> hold_time=<value> setup_chk_time=<value> setup_hold_time=<value> delay=<value> edge=[rise|fall|both] ref_edge=[rise|fall|both] vlth=<value> ref_vlth=<value> vhth=<value> ref_vhth=<value> time_window=[start1 stop1 start2 stop2 ....] <save=no|violation> <spice=no|yes> margin_stats=[yes|no] <subckt=[subckt1 subckt2....]> <fanout=all|gate|bulk> error_limit=<value> report=[violation|all]

SPICE Syntax

.cck title dyn_setuphold node=[node] ref_node=[node] setup_time=<value> hold_time=<value> setup_chk_time=<value> setup_hold_time=<value> delay=<value> edge=[rise|fall|both] ref_edge=[rise|fall|both] vlth=<value> ref_vlth=<value> vhth=<value> ref_vhth=<value> time_window=[start1 stop1 start2 stop2 ....] <save=no|violation> <spice=no|yes> margin_stats=[yes|no] <subckt=[subckt1 subckt2....]> <fanout=all|gate|bulk> error_limit=<value> report=[violation|all]

Description

Measures the timing of a signal net in comparison to a referenced (clock) net. It reports the setup or hold timing errors if the signal net transition happens within the specified violation window.

The violation window of the setup timing check is refTime + delay - setup_time and refTime + delay. The violation window for the hold timing check is refTime + delay and refTime + delay + hold_time. refTime is the transition time of the reference net.

ref_vhth and vhth parameters trigger the rising edge measurements, whereas ref_vlth and vlth parameters trigger the falling edge measurements.

If subcircuit parameter (subckt) is specified then the node (node) and reference node (ref_node) are considered local nodes to that subcircuit. That is, the nodes and reference nodes will belong to the instances of the specified subcircuit. Only one subckt value can be specified per check, with no wildcard.

If the subckt parameter is not specified then node and ref_node are considered as global nodes with hierarchical names starting from the top level.

The results are written to a file with the extension dynamic.xml, which can be viewed with a Web browser.

In the figure above, a setup or hold error is reported if the signal net transition occurs in the red marked area.

Arguments

node	Node to which the check is applied. Default is none.
ref_node	Name of the referenced clock (net). Wildcards are not supported.
setup_time	Setup time violation window. If specified, setup check is enabled. Default is 0.0 sec.
hold_time	Hold time violation window. If specified, hold check is enabled. Default is 0.0 sec.
delay	Delay time of the referenced signal. Default is 0.0 sec.
edge	Edge type of the signal net. Possible values are rise, fall, or both. Default is rise.
ref_edge	Edge type of the referenced signal net. Possible values are rise, fall, or both. Default is rise.
setup_chk_time	Specifies the setup time checking window. Spectre only checks the signal states within refTime+delay-setup_chk_time and refTime+delay window. Signal states outside the window are ignored. This argument is enabled only when setup check is enabled and the value of report is all. The specified value must be greater than setup_time. Default value is 2*setup_time.
hold_chk_time	Specifies the hold time checking window. Spectre only checks the signal states within refTime+delay+hold_chk_time and refTime+delay window. Signal states outside the window are ignored. This argument is enabled only when hold check is enabled and the value of report is all. The specified value must be greater than hold_time. Default value is 2*hold_time.
vlth	Low voltage threshold for the signal net. Default is 0.2v.
ref_vlth	Low voltage threshold for the referenced net. Default is 0.2v
vhth	High voltage threshold for the signal net. Default is 0.8v
ref_vhth	High voltage threshold for the referenced net. Default is 0.8v.
time_window	Time window to which the circuit check is applied. Multiple non-overlapping time windows are supported. Default time window is 0 to tend.
save	Specifies how to probe the signals specified within this circuit check. Possible values are: no: None of the signals in this circuit check are probed. This is the default value. violation: Automatically probe the signals with violations under this circuit check.
spice	Specifies whether to save the probed signals specified by the save parameter in the SPICE syntax. Possible values are: yes: Saves the signals in SPICE syntax no: Saves the signals in Spectre syntax. This is the default value.
margin_stats	Specifies whether or not to print the margin statistics. By default, margin statistics are not printed. Possible values are no and yes. The default value is no.
error_limit	Maximum number of errors to be reported. Default is 10000.
subckt	Instances of the specified subcircuit to which the circuit checks are applied. Default is none.
fanout	Fanout setting to filter node with specified connection. Possible values are all, gate, and bulk. Default is all. This option is supported only in Spectre FastSPICE mode.
report	Reports all checks or violations only. Possible values are all and violation. Default value is violation.

Example 1

Spectre Syntax

s4 dyn_setuphold node=["*"] edge=rise ref_node=“I9.I1.clk" ref_edge=rise setup_time=5e-11 vhth=0.5 ref_vhth=0.5

SPICE Syntax

.cck s4 dyn_setuphold node=["*"] edge=rise ref_node=“I9.I1.clk" ref_edge=rise setup_time=5e-11 vhth=0.5 ref_vhth=0.5

The above command reports any transition of signal node in the time window between 0.5ns before the signal clk rises.

Since subckt parameter is not specified, it will compare all nodes with ref_node I9.I1.sig_2 and report any violations.

The following is an example of the report that is displayed on the Web browser.

Example 2

Spectre Syntax

s1 dyn_setuphold node=["*"] edge=rise ref_node=“clk" ref_edge=rise setup_time=5e-11 vhth=0.5 ref_vhth=0.5 subckt=ckt1

SPICE Syntax

.cck s1 dyn_setuphold node=["*"] edge=rise ref_node=“clk" ref_edge=rise setup_time=5e-11 vhth=0.5 ref_vhth=0.5 subckt=ckt1

The above command reports any transition of the signal data in the time window between 0.5ns before the signal clk rises.

Since subckt=ckt1 is specified, it will compare all nodes in subckt ckt1 with ref_node sig_2 and report any violations. Note that node and ref_node belongs to same subckt ckt1.

The following is an example of the report that is displayed on the Web browser.

Related Topics

Dynamic Checks

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