Product Documentation
Virtuoso Design Planning and Analysis User Guide
Product Version IC23.1, November 2023

Pin Accessibility Checker

At advanced nodes, routing standard cell designs can be challenging because the cells are very closely packed and the density of the cells increases at lower nodes. Also, these designs follow complicated design rules. Routing such designs might involve several iterations.

The Pin Accessibility Checker is a standalone tool that lets you verify the routability of standard cells before you route the design. The Pin Accessibility Checker lets you ensure that the standard cells are correct-by-construction in terms of pin accessibility by the router. The tool performs a dynamic test by running the Cadence® InnovusTM router to check whether the router can access all pins without any DRC violations. You can also check for routing feasibility for various topologies in higher metal layers and in double-cut vias on critical nets.

Running the Pin Accessibility Checker early in the standard cell development phase helps avoid delays.

Related Topics

Running the Pin Accessibility Checker

Pin Accessibility Checker Form


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