B

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Pre-Compiled Libraries in Verilog In

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Verilog In uses the ncvlog parser to parse and translate the Verilog files into an Intermediate Representation (IR) that is stored in a 5.X architecture library. During analysis, for each module in the Verilog file, ncvlog creates a cellview in the 5.X library. The generated cellview has the following structure:

Verilog In compiles the source Verilog files in one go using ncvlog. A quick compilation without generation of any IR is performed on the library Verilog files to list all the modules in them. Whenever a library module is first referenced in the design, that module is compiled from the relevant Verilog library file and its IR is stored in the temporary work area.

If the same Verilog libraries are used over multiple runs of Verilog In it is much more advantageous to store the IRs of the Verilog files once for all in a pre-compiled library so that they can be used subsequently. In case of pre-compiled libraries, a Verilog library need not be compiled repeatedly to import designs.

When a destination IR library is specified, Verilog In compiles all libraries into the destination library in one go and then uses the pre-compiled library to import the design. Therefore in cases where the number of modules referenced from libraries is large, specifying a target IR library is advantageous even if the pre-compiled library is not required in future. In such cases, if the resources permit, you must try to make the destination IR library to point to the swap area of the machine for higher speed gain.