Import Options

Lets you specify the options available in Verilog In to import the schematic.

Global Net Options

Lets you specify the global nets and net expressions of the schematic imported by Verilog In.

Schematic Generation Options

Lets you specify the format of the schematic imported by Verilog In.

Verilog Files to Import

Lets you select the names of the Verilog files that contain the complete descriptions to import. You can type or select multiple files separated by a space.

To select the files, click the corresponding Browse button. In the Select File form, browse and select the files you want to import.

To select multiple files, hold down the Ctrl key and select the files.

Target Library Name

Specifies the Virtuoso Studio Design Environment library in which all the imported cells are to be placed.

If the library exists, Verilog In places the imported cells in it, else, Verilog In creates a new target library and places the imported cells in it.

Browse opens the Library Browser form. Clicking a library name in Library Browser puts that library name in the Target Library Name field.

Reference Libraries

Lets you reference the libraries that contain Virtuoso Studio Design Environment reference cells.

Typically, these reference cells are imported as part of another design or are ASIC library cells.

If a cell exists in a reference library with the same name as the module to import, Verilog In does not import the module.

If you want to generate a multi-sheet schematic, you must specify a reference library containing a sheet border and index sheet symbols (for example, the US_8ths library provided by Cadence).

The default reference libraries are sample and basic.

For incomplete designs, if the description of a module is not provided, but a symbol for the module exists in the reference library, it is used to create a structural view for the instantiating modules.

For more details on symbol selection, see Using Reference Libraries to Import Incomplete Designs.

Reference Symbol View Names

Lets you reference multiple symbol view names and find the instance master in the reference library.

Overwrite Options

This section specifies overwrite options for the cellviews to be generated by the import process.

Overwrite Existing Views

Overwrites existing views with a new version if the module to be imported already exists as a cell in the target library.

By default, this check box is not selected and Verilog In does not import a module if it already exists.

When the Overwrite Existing Views check box is selected, Verilog In imports the specified module and overwrites its existing version.

Overwrite Symbol Views

Overwrites the specified symbol view with a new symbol if the symbol of the module to be imported already exists in the target library.

By default, this option is set to None and Verilog In does not overwrite the symbol of a module if it already exists.

Set this option to any of the following values to specify which symbols you want to overwrite:

• None: Do not overwrite any existing symbol
• Created by VerilogIn: Overwrite only those existing symbols that were created by Verilog In. These symbols have the createdBy property set as VerilogIn. Symbols created by any other tool remain unaffected.

To view the createdBy property of any symbol, open it in Virtuoso Symbol Editor L and choose the Edit — Properties — Cellview menu option. The Edit Cellview Properties form that is displayed shows the createdBy property field.

• Created by TSG and Others: Overwrite the existing symbols created by the Text-to-Symbol generator or any other tool.
• All: Overwrite all the symbols existing in the target library and replace with those imported by Verilog In.

Import Modules as

This section provides the options to import the modules.

Structural Modules

Specifies the views that must be created for structural modules by Verilog In.

Possibe values:

• schematic creates a Virtuoso schematic view.
• netlist creates a Virtuoso netlist view.
• functional creates a Virtuoso functional view.
• schematic and functional creates both a Virtuoso schematic view and a Virtuoso functional view.
• netlist and functional creates both a Virtuoso netlist and a Virtuoso functional view.

If you use the schematic option for a big design containing a large number of gates or huge vector nets, it can take several hours to complete the processing and can require a large amount of memory. In this case, you can create a quick schematic without routed nets and where the connectivity is indicated by names.

For generating such a place-only schematic, disable Full Place and Route in the Schematic Generation Options tab or specify the Verilog In +DUMB_SCH option in the -f Options file.

If you want to maintain the placement and routing information in the schematic, split your Verilog design into sub-designs before you import it using the schematic option.

If you want only the connectivity of the design and not the graphics, use the netlist option instead of the schematic option.

Verilog Cell Modules

Specifies what to do if a module is described as a Verilog HDL cell in the input file.

• Create Symbol Only Creates only a symbol view for the Verilog HDL cell.
• Import: Imports the Verilog HDL cell as a view, and creates the database for the view.
• Import As Functional: Imports the Verilog HDL cell as a functional view.

Schematic View Name

Specifies the name for the schematic view to be created in the target library. The default view is schematic.

Netlist View Name

Specifies the name for the netlist view to be created in the target library. The default view is netlist.

Functional View Name

Specifies the name for the functional view to be created in the target library. The default view is functional.

Symbol View Name

Specifies the name for the symbol view to be created in the target library. The default view is symbol.

Filter Modules

This section specifies options to filter modules in the schematic.

Ignore Modules File

Specifies the text file that lists modules which you do not want to import. Modules underneath these modules in the design hierarchy are imported, unless they too are listed in this file. Create this file with a text editor and list one module for each line.

For example, given a module hierarchy as follows:

If the ignore modules file contains:

B
C

Verilog In imports the modules A, F, D, G, and E.

If a module is listed in the ignore modules file and Verilog In does not find a symbol for the module in the target or reference libraries, Verilog In creates a symbol for the module.

Import Modules File

Specifies the text file, which lists the modules that you need to import. Only the modules listed in the file are imported. The modules underneath these modules in the design hierarchy are marked as IGNORE and are not imported. Create this file with a text editor and list one module for each line.

If the specified text file is empty, all the modules in Verilog In netlists are marked as IGNORE and none of the modules is imported. Only the symbol view is created for the modules marked as IGNORE while processing the specified text file.

Library Pre-Compilation Options

This section provides the options to specify pre-compiled libraries.

Pre Compiled Verilog Library

Specifies the name of the pre-compiled library to be used while importing a design. Multiple pre-compiled libraries can be specified by separating them with spaces.

HDL View Name

Specifies the view in the pre-compiled library that is used to find the IR for the cell while using pre-compiled libraries.

When pre-compiled libraries are created, use this option to specify the view in which the IR of the module is saved.

The default view name is hdl.

Target Compile Library Name

Specifies the 5.X library where the Intermediate Representation (IR) produced for the Verilog libraries specified using the -v and -y options that are located. You can also click the Browse button to open the library browser and select a target library.

Compile Verilog Library Only

Compiles pre-compiled libraries without importing the design.

Other Input Options

This section lets you specify additional input options.

-f Options

Specifies the names of the files that contain Verilog In options, such as -y, -v, and other command line options. Verilog In adds these options to the command line options when it imports the file. These option files let you enter the same arguments simultaneously for multiple files. The Verilog In -f option files are similar to the -f option in Verilog-XL.

-v Options

Specifies the names of the Verilog files needed to compile the design. The reference design files can be given as -v options.

-y Options

Specifies the name of the Verilog library file.

Library Extension

Specifies a suffix that identifies Verilog files in the path to the Verilog Library. Different organizations use different extensions, such as .v (default), .V, .vlog, or .verilog.

Other Output Options

This section lets you specify additional output options.

Log File

Specifies the file that logs the import status of each module being imported. For more information about the log file, see Output Files Created by Verilog In. The default log file is ./verilogIn.log.

Work Area

Specifies the directory in which Verilog In stores internal data.

This option is useful for importing large designs when space in the /tmp directory is limited. When you quit Verilog In, the software deletes the files in this directory.

Name Map Table

Specifies the name of the map table file that correlates the original names to the new mapped names. Original names are escaped names that are legal in Verilog but not in Virtuoso Studio Design Environment.

The default filename is./verilogIn.map.table (stored in the current directory).

Process Technology File

Specifies whether you want to create a technology file during import. If you deselect this option, no tech.db is created during import. This option can also be specified from the command line using the -notechfile switch.

You can also specify this option using the processTechFile environment variable in one of the following ways:

• In the CIW, type
  envSetVal("ihdl" "processTechFile" 'boolean t).
• In the.cdsenv file, specify
  ihdl processTechFile boolean t/nil.

Global Nets

This section provides options to specify names for a global power net, a global ground net, and other global signals in the schematic.

Power Net Name

Specifies the name for the global power signal In the Verilog design. You can specify only one power net name.

The power net name that you specify is recognized throughout all modules in the design. All 'b1 assignments are replaced by this power net in the schematic.

Connect Power Net by Name

Connects the power net by the specified power net name. Use this option to import a logical netlist with the power net connected by name, instead of a physical wire. Enabling the options to connect by name does not physically connect the nets, but the connections are established by names. In this case, the nets are not routed. One of the cases where you enable these options is when you import CPF where nets can be connected to different power supplies.

Ground Net Name

Specifies the name for the global ground signal in the Verilog design. You can specify only one ground net name. The ground net name that you specify is recognized throughout all the modules in the design. All 'b0 assignments are replaced by this power net in the schematic.

Connect Ground Net by Name

Connects the ground net by the specified ground net name. Use this option to import a logical netlist with the ground net connected by name, instead of a physical wire. Enabling the options to connect by name does not physically connect the nets, but the connections are established by names. In this case, the nets are not routed. One of the cases where you enable these options is when you import CPF where nets can be connected to different power supplies.

Global Signals

Specifies the names of global signals in the Verilog design other than power and ground. The global signals that you specify are appended in the design with the exclamation character (!) to make those signals global. You can specify multiple global signals. All pins and nets, except power and ground pins and nets, have the default signal name set to signal. For power pins and nets, the default signal name is supply, and for ground pins and nets, the default signal name is ground.

Connect Global Signals by Name

Connects global signals by the specified global signals name. Use this option to import a logical netlist with the global signals connected by name, instead of a physical wire. Enabling the options to connect by name does not physically connect the nets, but the connections are established by names. In this case, the nets are not routed. One of the cases where you enable these options is when you import CPF where nets can be connected to different power supplies.

Create Net Expression

This section lets you specify options to create net expressions. If you select this option, you must specify valid values for Property Name for Power Net and Property Name for Ground Net.

Create Net Expression

Lets you translate tie highs and tie lows so that net expression can be created on the power and ground net.

When not selected, Verilog connects the port to either a power or a ground signal in case of constant port connectivity.

Property Name for Power Net

Specifies a different net expression property name for power nets. The default is vdd.

Property Name for Ground Net

Specifies a different net expression property name for ground nets. The default is gnd.

Full Place and Route

Specifies placement and routing options for the schematic.

Lets you generate a schematic with full placement and routing when the number of instances or ports in the file being imported are within the limits specified in the Instances Less Than or Ports Less Than fields.

If the number of instances or ports exceed the specified number, Verilog In generates a place-only schematic in which the nets are not routed and the connectivity is indicated by name.

Deselect this check box to create a place-only schematic, irrespective of the number of instances or ports. When you deselect the check box, the Instances Less Than and Ports Less Than fields become disabled.

• If you select Full Place and Route and the design being imported has a large number of instances and ports, the schematic generation process can take significant time to place and route the instances and nets.
• To always create a place-only schematic, you can specify the Verilog In +DUMB_SCH option in the -f Options file or deselect the Full Place and Route check box.
• Place-only schematics are recommended for importing large benchmarking designs.

Instances Less Than

Specifies the maximum number of instances in the file being imported when the Full Place and Route check box is selected.

If the file has more than the specified number of instances, Verilog In generates a place-only schematic.

The default value is 20000.

Environment variable: pnrMaxInst.

For information on the corresponding parameters for the ihdl_parameter file, see Verilog In Command-Line Mode.

Ports Less Than

Specifies the maximum number of ports in the file being imported when the Full Place and Route check box is selected. If the file has more than the specified number of ports, Verilog In generates a place-only schematic.

These fields specify the default value and the environment variable of these options, which are typically set in .cdnsenv.

The default value is 5000.

Environment variable: pnrMaxPort.

For information on the corresponding parameters for the ihdl_parameter file, see Verilog In Command-Line Mode.

Pin Placement

Specifies the direction for placing pins in the schematic that Verilog In generates using the pin-placement options.

Placement Configuration

Specifies the configuration to be used for pin-placement in the schematic.

• Left and Right Side
  Places all the pins on the left and right sides of the symbols, usually with input pins on the left, and inout pins and output pins on the right.
• All Sides
  Places the pins on any side.
• Pin Placement File
  Enables Pin Placement File Name field.
• Pin Placement File Name
  Specifies the direction of each pin in the imported module.

The syntax of the pin-direction declaration in a pin-placement file includes the module name, the pin direction, and the pin name list. The values for the direction are top, bottom, left, or right. The pin names are specified as a list of strings separated by spaces and are the existent pin names on the given module name. You can repeat this statement many times, but do not duplicate the same module-pin pair.

The syntax of entries in a pin placement file is as follows:

pin placement := module direction pinNames

The pin names in the pin-placement file must match the names specified in the port list. Additionally, the pin names must not contain spaces, except escaped names.

The following is an example entry in a pin-placement file:

pin_placement := test_module top B C D[0] {A,B,A[2:3],D,E}

For compatibility with previous product versions, the pin-placement functionality also supports a comma-separated pin-placement file. The following is an example entry in a comma-separated file:

pin_placement := test4, top, a, b

Based on the format of the entries in the pin-placement file, the following behavior of the pin-placement functionality is observed:

Format

Behavior

• A space-separated file containing scalars, vectors, and bundles in the correct syntax

• Places the pins as expected.

• A comma-separated file containing only scalars

• Places the pins as expected.

• An incorrect comma-separated file that contains vectors and bundles, or incorrect syntax

• Does not place the pins as expected. Only the import process is completed.

• A space-separated file where the syntax is incorrect

• Causes an error and exits the import process.

Reference Schematic/Symbol View for Inherited Connections

This section lets you specify a list of views that can be looked up by the tool.

List of Views

Specifies the separated schematic or symbol views in the List of Views field, which the tool can look up for missing terminals on an instance line in the input Verilog file.

It is possible that an instance line in the Verilog file has more terminals than the number of terminals specified on the identified instance symbol master.

In this case, the tool uses the schematic or symbol views specified in the Reference Schematic/Symbol View For Inherited Connections field to look for the required additional terminals.

The reference schematic views can contain terminals or nets with net expressions whose names match the names of the additional terminals on the instance line.

The tool extracts the netExpression property name from those inherited terminals or nets. It then sets the netSet property on the instance for the missing terminals, as described below.

• The netSet property name is set using the netExpression property name obtained from the reference schematic
• The netSet property value is set from the net connected to the instance line in the Verilog file

For example, you can use this field when you want to import a physical Verilog netlist with power-ground terminals on an instance line, where the corresponding symbol master does not have the power-ground terminals.

In this case, Verilog In checks if the power-ground terminals or nets exist in the reference schematic/symbol view list. If the corresponding terminals or nets exist and are inherited, the application creates the netSet properties for these power-ground terminals on the instances in the schematic.

Through Cellview to be Used for Port Shorts

This section specifies the library, cell, and view name of the component to be used between shorted ports.

Library

Lets you specify the library name of the component to be used between shorted ports.

When the input and output ports of a module in the input Verilog design are shorted, Verilog In puts the default symbol called cds_thru between the shorted ports. The symbol cds_thru is put instead of the patch symbol used for other shorts to avoid shorted terminals connectivity extraction errors from Virtuoso Schematic Editor.

The default location of this symbol is basic.

You can customize the location of the symbol from the Schematic Generation Option form. You can also click the Browse button and select the design from Library Browser.

Cell

Lets you specify the cell name of the component to be used between shorted ports.

The default location of this symbol is cds_thru.

View

Lets you specify the view name of the component to be used between shorted ports.

The default location of this symbol is symbol.

Continuous Assignment Symbol

Specifies the library, cell, and view names for the patch symbol to avoid net shorting. Net shorting happens whenever you use an assign statement, such as assign a=b; in which both a and b are local nets.

You can also click the Browse button and select the design from Library Browser.

Library

Lets you specify the library name.

The default location of this symbol is the basic library.

Cell

Lets you specify the cell name.

The default location of this symbol is the patch library.

View

Lets you specify the view name.

The default location of this symbol is the symbol library.

Advanced Schematic Generation Options

This section lets you set advanced schematic generation options.

Generate Square Schematics

Specifies whether to square the schematic. Deselect this option if you do not want to have Verilog In manipulate rows and columns of devices to make a rectangular schematic into a square one.

By default, this option is enabled.

Minimize Crossovers

Specifies whether to minimize crossover of nets. Select this option to minimize crossovers of nets.

By default, this option is disabled.

Optimize Wire Label Locations

Specifies whether to override default label placement.

Select this option to override default label placement, which keeps overlap of segments or labels to a minimum, in favor of fast placement, which places labels of segments at the midpoint without checking for the minimum overlap.

By default, this option is disabled.

Extract Schematics

Specifies whether to extract the schematic. Select this option to extract the schematic, that is, to have Verilog In look for errors and warnings in the schematic written into the Open Access database format. An extracted schematic shows blinking markers for the errors or warnings in the schematic view.

By default, this option is enabled.

Ignore Extra Pins on Symbol

Lets you control the selection of symbols from the reference libraries. If this button is selected and Verilog In finds a reference symbol with the same name as specified in the Verilog design, the symbol is picked up. The pins not referred remain unconnected in the schematic.

By default, this option is disabled.

The symbol is picked up even if all its pins are not used.

To get the pin symbols from the reference library, set the following environment variables:

ihdl pin_master_cells string "ipin opin iopin"

The pin_master_cells specifies the cell names to be used for IO pins. The sequence for specifying the pin names is input, output, and input-output pins. The default value is "ipin opin iopin".

ihdl pin_master_basic_lib boolean nil

The pin_master_basic_lib specifies whether the symbol views of pins must be taken from the basic library or from the reference libraries.

The default value is t.

When set to t, the offsheet symbol views of pins are taken from the basic library and the symbol views of pins are taken from the reference libraries. If any of the symbol views are not found in the respective libraries, then the symbol views are created in the destination library.

When set to nil, all symbol views of pins are taken from the reference libraries. The cell names for pins are determined by the pin_master_cells variable.

No Dummy Nets in Netlist View

Specifies whether to connect dummy nets to unconnected pins of instances. Deselect this option to connect dummy nets named _NeTt_1,2,3.... in the netlist view to unconnected pins of instances. By default, this option is disabled.

This option only works for netlist view and not for schematic view. For schematic view, all unconnected pins on instances are always connected to dummy nets named NeTt_1,2,3....

Verbose

Lets you print detailed status messages while the schematic is being partitioned and routed. Select this option to print detailed messages. By default, this option is disabled.

Create Snap Space Properties

Enables or disables the creation of snap space properties. Snap space can be defined as the minimum distance the cursor moves, in user units. The default distance (0.0625) is equal to half the default grid spacing distance. When this option is set to 0, then the x-y Snap Space properties are not created on the cellview.

The default is 1 (enabled).

Connect By Name Nets

Lets you specify the list of scalar nets that need to be connected by name instead of physical wires. If a net specified in this field is a part of a bundle then all the nets in the bundle are connected by name.

Text to Symbol Generator Files

Specifies a space-separated list of tsg files to be used by Verilog In to generate symbols in the target library. Verilog In internally runs the Text-to-Symbol generator, a tool that reads the symbol descriptions given in the tsg files to create symbol views.

If the tsg files are used, the direction of pins specified by the Pin Placement option is ignored. Pins are placed on symbols as defined in the tsg files.

For more details on the Text-to-Symbol generator and the tsg files, see Text-to-Symbol Generator.

Schematic Dimensions

This section provides options to let you set schematic dimensions.

Sheet Symbol

Specifies the symbol that controls the size and page orientation of the sheet on which the schematic is to be made. Valid entries are the names of customer-designed sheet symbols and sheet symbols offered by Virtuoso Studio Design Environment.

A selection of sample sheet symbols is shipped with Virtuoso Studio Design Environment in the install_dir/tools/dfII/etc/cdslib/sheets/US_8ths library. These symbols include metric sheet symbols A0 through A4 and sheet symbols for the traditional A, A.book (vertical orientation), B, C, D, E, and F sizes.

The library containing the sheet symbol entered in this field must be in your cds.lib file so that Verilog In can find the correct information.

If the Sheet Symbol is none, Verilog In makes a single sheet schematic.

If a specific sheet symbol size is provided, and Verilog In cannot fit the schematic onto one sheet, it creates a multisheet schematic. A multisheet schematic has one index sheet and many schematic sheets.

The view with the index sheet for the schematic has the same name as the Verilog module. The schematic sheets are numbered cellname.sheetnnn where cellname is the Verilog cell name and nnn is the sheet number.

The default is none.

For information about working with sheet symbols and multi-sheet schematics, refer to Virtuoso Schematic Editor User Guide.

Maximum Number of Rows

Specifies the maximum number of rows that Verilog In places on each sheet. Verilog In uses this option only on a multi-sheet schematic. The value must be an integer from 1 to 1024.

Depending on the size of the instance symbols and the size of the sheet, Verilog In might not be able to place the maximum number of rows on a sheet. If you specify a value that is too large for the size of the instance symbols and the size of the sheet, Verilog In places as many rows as fit on each sheet up to the maximum of 1024.

The default is 1024.

Maximum Number of Columns

Specifies the maximum number of columns that Verilog In places on each sheet. Verilog In uses this option only on a multi-sheet schematic. The value must be an integer from 1 to 1024.

Depending on the size of the instance symbols and the size of the sheet, Verilog In might not be able to place the maximum number of columns on a sheet. If you specify a value that is too large for the size of the instance symbols and the size of the sheet, Verilog In places as many columns as fit on each sheet up to the maximum of 1024.

The default is 1024.

Font Height

Controls the size of the font used for pin, wire, and instance labels. The value must be a real value between 0.0375 and 0.125. The wire and instance labels use the font size specified in Font Height. Pin labels are scaled down to 75 percent of the specified size.

The default is 0.0625.

Line To Line Spacing

Specifies the spacing in inches between nets flowing in a channel for each sheet. The spacing for net segments connected to instance pins depends on the pins placed on symbols of the instances. Line To Line Spacing is used for all other net segments. The value must be a decimal number in the range of 0.125 to 0.74 inches.

The default is 0.2.

Line To Line Component Spacing

Specifies the spacing in inches between a component and the nearest net flowing in a channel. The value must be a decimal number in the range of 0.125 to 0.74 inches.

The default is 0.5.

Component Density

Lets you control the density of the schematic. The value must be an integer from 0 to 100, where 100 is the most dense and 0 is the least dense.

The default is 0.