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Introduction to Verilog In

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Verilog In lets you import a Verilog Hardware Description Language (HDL) file into the Virtuoso Studio Design Environment. Using this tool, you can create schematic, symbol, and functional views corresponding to the modules in the Verilog file. Verilog In also lets you create netlist views, which are similar to schematics but without the placement and routing information for the design objects.

This topic is aimed at the designers of digital circuits and assumes that you are familiar with:

• The Virtuoso Studio Design Environment and application infrastructure mechanisms designed to support consistent operations between all Cadence tools.
• The applications used to design and develop integrated circuits in the Virtuoso Studio Design Environment, notably Virtuoso Schematic Editor.