Prerequisites for Using Verilog In

Verilog In imports a design from a Verilog HDL file into a Virtuoso library.

Before you use Verilog In, do the following:

• Create the required Verilog design file containing a complete Verilog HDL description file or set of files.
• Ensure that the design has been successfully compiled by the Verilog compiler.

Licensing Requirements

Verilog In searches for the following licenses in the specified order and checks out one of them:

• 1 license of Virtuoso^® Schematic Editor L
• 1 license of Virtuoso^® Schematic Editor XL
• 1 license of Virtuoso^® Layout Suite L
• 1 license of Virtuoso^® Layout Suite XL
• 4 tokens of Virtuoso^® Layout Suite GXL

For information on licensing in the Virtuoso Studio Design Environment, see Configuring the Virtuoso Studio Design Environment.

Memory Requirements

The following table lists the memory and swap requirements for your hardware to be able to run Verilog In against different sizes of the input Verilog design. The design size column indicates the number of instances in the design.

Design size	No. of Modules	Memory Used (Netlist)	Memory Used (Schematic)	Workarea Space Used
210K	141	15.3M	18M	10.7M
341K	3	19.2 M	466M	3.4M
1.8M	328	33.5M	58M	30.3M
2.1M	3	87M	139M	9.2M
3M	9	58M	--	42M
5M	13	56M	--	31M
5M	2265	33M	66M	461M
5.3M	3	61M	258M	22M
26M	2391	151M	236M	243M
83M	383	275M	663M	289M

Related Topics

Classification of Modules in Verilog In

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