Escaped Name Mapping in Verilog In
This topic describes how Verilog In handles escaped names. Escaped names are names preceded by a backslash and followed by a space. The advantage of using escaped names is that certain characters that are illegal in Verilog can be used in escaped names.
- The escaped names are mapped into legal names in the OpenAccess format and this information is stored in a file.
- Verilog In follows the Cadence standard name mapping scheme that is recognized by other Cadence tools.
- You can specify the name of the file in which you want the mapping information to be stored.
- The Verilog analyzer handles escaped names in certain cases. Information about these is not stored in the file.
In 4.3.4, Verilog In used its own name mapping rules, but 4.4 onwards it uses the standard name mapping rules as described in Cadence Application Infrastructure. The identifiers are mapped from the OA name space to the Verilog name space. You can use the search and replace capabilities of Virtuoso to customize the mapping on generated schematics.
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