Parameters and Defparams in Verilog In
Modules containing parameters and defparams are treated as structural. However, functional views are created for the following exceptional cases:
- If the datatype of the value for parameter or defparam is other than decimal integer values, real values, and strings.
- If the parameter or defparam contains any arithmetic or logical expressions.
- If the parameter or defparam contains any identifier defined earlier by parameter statement.
- If parameters are used in the port declaration or net declaration.
- The inline parameter instantiation is used, but the source file containing the module definition is not given.
The
paramOrder property is not be added to the schematic or symbol imported and the user may add this manually. For more details about paramOrder, see Adding Simulation Properties.Return to top