Guidelines for Creating and Editing Symbols
This topic describes how to create or edit symbols using Virtuoso Schematic Editor before you import the Verilog design. These guidelines are for symbols that are used in schematics created by Verilog In.
If you do not follow these guidelines when creating or editing symbols, Verilog In might not create schematics, or might create schematics that are incorrect or off-grid. Also, nets might overlap symbols and symbol labels might overlap nets or net labels.
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To prevent extraction errors, make sure the snap spacing is
10database units (dbu) or greater.
When creating schematics, Verilog In takes the snap spacing for schematics and symbols from the propertyxSnapSpacingon theschematicviewType in the target library. Ideally, snap spacing must be an even number of dbu. -
To ensure that schematics are on-grid, check that the snap spacing of the target library and that of the symbols in the reference libraries are the same.
If this is not possible, make sure the symbols in the reference libraries have a snap spacing that is a multiple of the snap spacing of the target library. -
To ensure that schematics are correct, check that the outer edges of all pin figures on each side of the symbol are on the same line meaning pin figures cannot be recessed from other pin figures and are abutting the bounding box.
The bounding box is the smallest box enclosing all pin figures and all shapes on the Device-Drawing Layer Purpose pair. Also, make sure that no symbol figures are beyond the pin figures on either side of the symbol shape. You must also specify a unique pin access direction on the pins of the symbol; otherwise, a net might be connected to a pin from a wrong direction. -
Snap spacing is set lower than
10 dbuin theschematicviewType in the target library. -
Snap spacing in the symbol is not a multiple of the snap spacing in the target.
If the pins of a symbol are too close, the input/output pins of the cellview in which the symbol is placed may overlap. In such cases, the input/output pins are displaced and connected by name to the connecting net. -
To ensure that schematics are on-grid, make sure all marked lengths are a multiple of the snap space, including the pin-to-pin distances and the origin-to-pin distance.
Verilog In places the origin of the Virtuoso Symbol on the snap grid. If all marked lengths are not multiples of the snap space, the schematic is off-grid. Usually this is not a problem because the Symbol Editor automatically imposes this restriction. Problems might occur only if the snap space of the symbol has been changed during or after editing the symbol.
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