Guidelines for Design Modification in Verilog In

The following topic describes how Verilog In imports data and how to modify the design before and after importing it.

• You must modify Verilog descriptions that are order-dependent with respect to compiler directives (for example, 'define) to remove this order dependency before they are imported (or entered using Virtuoso Schematic Editor).
  All compiler directives necessary for the correct interpretation of a module must be contained in the textual cellview describing that module in the Virtuoso Studio Design Environment database. You can use the include file facility to include a set of 'define statements from a single file with all modules that use the resulting text macros.
• Verilog-XL include files are not managed in Virtuoso Studio Design Environment. You must manage included files in your own directories.
  You must specify the full path names for included files or other required files, such as memory files, in Verilog descriptions.
• Verilog In inserts files that are included by the 'include directive into the module.
  Verilog In creates a schematic if possible. Otherwise Verilog In creates a functional view, which does not display the included file.
• An imported schematic that instantiates a lower level module uses an improper symbol for the lower level module when:
  • A symbol exists for the lower level module before the import begins
  • A mismatch exists between the ports on the lower level module that is imported and the existing symbol of the cell with which the lower level module is associated
  
  You must either delete the existing symbols from your design file before you import the lower-level module or turn on the Overwrite Existing Views option on the Verilog In form.
• Verilog In might create incorrect schematics under certain conditions. In these cases, Verilog In reports in the log file that a problem occurred while creating or checking connectivity of the schematic.
  You must edit and correct the schematic.
• Verilog In saves the following information as properties on schematic views:
  • The 'timescale directive
  • The rise and fall delay on Verilog primitives
  • The tri, tri0, tri1, trireg, wand, wor, triand, trior, supply0, and supply1 net declarations
• Sometimes Verilog In creates schematics with objects that are off-grid.
  After you import the Verilog design, you might need to adjust the snap spacing to edit and manipulate these objects. For example, if symbols in a schematic have a different snap spacing from the schematic, the symbols might be off-grid. See Guidelines for Creating and Editing Symbols for information about creating and editing symbols before you import the Verilog design.

Related Topics

Guidelines for Creating and Editing Symbols

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