Output Files Created by Verilog In

In addition to creating a Virtuoso schematic or a Virtuoso netlist, Verilog In creates a log file named verilogIn.log. Verilog In also creates the verilogIn.map.table file, which contains the original escaped names and the corresponding mapped names.

The verilogIn.log File

The verilogIn.log file is generated after the import process is complete. The contents of this file include:

• The module name
• Verification that the file was imported
  (If the module was not imported, the log describes the reason.)
• Any warnings related to the module

A sample verilogIn.log file contains entries, such as the following:

@(#)$CDS: ihdl version 6.1.6-64b 03/19/2014 21:16 (sjfnl116) $  Fri Mar 21 13:24:45 2014

Checked in functional view U_MUX_2_NONINV. UDP description found

Checked in functional view MUX21LB. Module is a cell

Checked in functional view U_FFD_P_RB_NOTI. UDP description found

Checked in functional view FD2. Module is a cell

Checked in functional view AN2. Module is a cell

Checked in symbol view_name

Checked in functional view counter_gnd. User specification

End of Logfile

The verilogIn.map.table File

The verilogIn.map.table file is created by Verilog In to store information about the original escaped names and the mapped names.

A sample verilogIn.map.table file contains entries such as the following:  

VerilogIn Version 4.4.1 Wed Feb 12 17:18:30 1997
Original Name Mapped Name
*****Map table for module x*****
\a?*b a?*b
\A*B A*B