Exceptions in Data Import by Verilog In

This topic describes data that is not imported by Verilog In.

• If Verilog In finds a cell in a reference library that has the same name as the module, Verilog In checks the names, the number of ports, and the port direction of both the module and the existing cell and does not import the module.
  If any of these do not match, Verilog In reports an error in the verilogIn.log file.
• If your design refers to library modules that have identical names, Verilog In imports only the first module found.
  Therefore, if you want to import both modules, you must change the name and the references of one module. You cannot use the Verilog-XL command-line option +liborder as a work around because Verilog In does not support that option.
• If Verilog In finds a cell in the target library that has the same name and same view as the module, Verilog In does not import the module unless the Overwrite Existing Views option is on.
• If Verilog In finds the symbol view of a cell in the target library, it does not import the symbol view unless an appropriate value is set for the Overwrite Symbol Views option.
• If Verilog In identifies a module as structural, Verilog In does not import any comments inside or outside the module definition boundaries.
• If Verilog In identifies a module as functional, Verilog In does not import any text from within the module or text that follows the endmodule keyword, except for 'endcelldefine.
  Compiler directives that precede the module definition are shown in the functional view. Except for 'endcelldefine, compiler directives that follow the endmodule keyword are imported into different cells.
• Verilog In does not import modules that are split across multiple files.
• Verilog In imports modules with parameterized ports as functional views but does not create a symbol for them.

Before using Verilog In, be aware of the following problem that might result in loss of data.