Components of the ihdl Command
The ihdl command includes three main components, the ihdl_files file, -f options and the ihdl_parameter File.
The ihdl_files File
You specify the ihdl_files file in the startup command. The ihdl_files file contains option settings, as follows:
-param ihdl_parameter
-v verilog_library_file.v
-y verilog_library_path
Options Specified with -f in the ihdl Command
You can specify the following Verilog In options in -f files or as command line arguments.
Verilog In options are not case sensitive. For example, -help and -HELP are considered the same.
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-HELP
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Prints an online description about command line options.
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-IHDL_ALLOW_GLOBALS
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Allows global signals.
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-VERSION
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Prints the version number.
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-NOCOPYRIGHT
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Suppresses the printing of the copyright banner.
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+NO_PLACE
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Creates a schematic without any placement and routing information.
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-NO_PORT_CHECK
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Does not check sizes.
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-OVER_DENSE
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Creates high-density schematics.
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-IGNOREEXTRAPINS
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Ignores extra pins in picking up reference symbols.
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-F <arg>
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Specifies a command line from a file.
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-V <arg>
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Specifies the name of the Verilog library file.
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-Y <arg>
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Specifies the name of the Verilog library directory.
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-PRECOMPILELIBRARY <arg>
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Specifies the pre-compiled library to be used for importing the design.
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-DESTIRLIB <arg>
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Specifies the name of the destination library where the pre compiled library gets created. If you specify more than one destination library, then only the first one is used and the others are ignored.
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-COMPILEONLY
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Specifies that pre-compiled libraries must be compiled only for libraries specified using -v and -y options and not import the entire design.
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-PARAM <arg>
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Specifies the name of a schematic parameter file.
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+DUMB_SCH
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Creates a schematic that does not indicate nets or connectivity by name.
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-NOSQUARE
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Does not square the schematic; that is, does not manipulate rows and columns of devices to convert a rectangular schematic into a square one.
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-MIN_CROSSOVERS
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Minimizes crossovers of nets.
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-FAST_LABELS
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Enables faster placement of labels. When this option is on, Verilog In labels segments at the midpoint and does not check for minimum overlap.
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+NOXTRSCH
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Does not extract the schematic; that is, does not find errors and warnings that have been written into the Cadence C-level database access format.
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-DEFINE <macro>
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Defines a macro from the command line.
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-cdslib <filename>
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Specifies the cdslib file.
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-hdlvar <filename>
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Specifies the name and location of the hdl.var file, which contains the variables and settings for the compiler, elaborator, and simulator.
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-VERBOSE
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Specifies whether to print detailed status messages while the schematic is being partitioned and routed.
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-NOEXTRANETS
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Specifies whether or not dummy nets are present on unconnected pins of instances. This option only works for netlist view and not for schematic view.
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The ihdl_parameter File
The ihdl_files file contains a call to the ihdl_parameter file. The ihdl_parameter file specifies the parameters for both the Verilog In and the Schematic Generation Options forms.
Example
-- Verilog In Form
dest_sch_lib := targetn
ref_lib_list := basic, sample, US_8ths
ignore_node_file := <ignore_node_file_name>
import_if_exists := 1
import_cells := 0
import_lib_cells := 0
structural_views := 5
schematic_view_name := schematic
functional_view_name := functional
netlist_view_name := netlist
symbol_view_name := symbol
overwrite_symbol := 1
log_file_name := ./verilogIn.log
map_file_name := ./verilogIn.map.table
work_area := <directory_name>
power_net := VDD!
ground_net := GND!
glob_sig_names := net1,net2
-- Schematic Generation Options Form
sheet_symbol := Asize
page_row_limit := 512
page_col_limit := 256
label_height := 12
line_line_spacing := 0.2
line_component_spacing := 0.5
density_level := 0
pin_placement := file, pin_placement_file
client := synthesis
alias_module := cds_alias
cont_assign_symbol := basic patch symbol
ref_sch_list := schematic, sch
pnr_max_inst := 20000
pnr_max_port := 5000
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