Product Documentation
Verilog In User Guide
Product Version IC23.1, November 2023

Parameters Specified in the ihdl_parameter File

The parameters that you specify in the ihdl_parameter file correspond to option fields in the Verilog In form as shown in the following table:

Tab Field Parameter

Import Options

Target Library Name

dest_sch_lib

Reference Libraries

ref_lib_list

HDL View Name

hdl_view_name

Ignore Modules File

ignore_node_file

Import Modules File

import_mod_file

Import Structural Models As

structural_views

Structural View Names

OA structural view names

Log File

log_file_name

Work Area

work_area  

Name Map Table

map_file_name

Overwrite Existing Views

import_if_exists

Overwrite Symbol

overwrite_symbol

Verilog Cell Modules

import_cells

Verilog Cell Modules

import_lib_cells

enable_explicit_port_checking

create_ifc_func_view

Global Net Options

Power Net Name

power_net

Ground Net Name

ground_net

Global Signals

glob_sig_names

Schematic Generation

Sheet Symbol

sheet_symbol

Maximum Number Of Rows

page_row_limit

Maximum Number Of Columns

page_col_limit

Font Height

label_height

Line To Line Spacing

line_line_spacing

Line To Component Spacing

line_component_spacing

Component Density

density_level

Pin Placement

pin_placement

Through CellView For Shorted Ports

cds_thru_symbol

Create Snap Space Properties

create_snap_space_prop

Reference Views for Inherited Connections

ref_sch_list

Environment Variable: refSchList

Instances Less Than

pnr_max_inst

Ports Less Than

pnr_max_port


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