Glossary
A quantity that represents the potential across two terminals.
Anything evaluated by the analog simulator such as an analog simultaneous statement.
A body associated with an entity declaration to describe the internal organization or operation of a design entity. An architecture body is used to describe the behavior, data flow, or structure of a design entity. There can be multiple architecture associated with a single entity.
A definition of some characteristic of a named entity. Some attributes are predefined for types, ranges, values, signals, and functions. The remaining attributes are user defined and are always constants.
The representation of a portion of the hierarchy of a design. A block is either an external block or an internal block.
A statement that notifies the analog solver to be prepared to deal with a discontinuity in an analog value at the next analog solution point. During a QUIESCENT_DOMAIN (DC solution), the break statement can also force named quantities to assume specified reset values.
A level of abstraction at which a designer can perform realistic simulation of a full system:
1) Synthesis: Without any detailed timing information like FPGAs.
2) Simulation: Accurately simulates the chip.
Interconnected active and passive components such as resistors and capacitors.
Describes instances of an entity and connects signals, quantities, and terminals to the ports of the instances.
A statement that executes asynchronously, with no defined relative order. Concurrent statements are used for dataflow and structural descriptions.
One that obeys Kirchhoff's laws.
An object whose value cannot be changed. Constants must be declared before they are used in models.
A simulation in which values are a continuous function of time.
A simulation in which all changes to the system occur at precise simulation times.
The former Cadence Design Framework II, which has now become Virtuoso Design Environment in IC 6.1.
A definition of the interface between a given design entity and the environment in which it is used. Entities can also specify declarations and statements that are part of the design entity. A given entity declaration can be shared by many design entities, each of which has a different architecture. Thus, an entity declaration can potentially represent a class of design entities, each with the same interface.
A collection of sequential statements that are executed for their result.
An interface constant declared in the block header of a block statement, a component declaration, or an entity declaration. Generics provide a channel for static information to be communicated to a block from its environment. Unlike constants, however, the value of a generic can be supplied externally, either in a component instantiation statement or in a configuration specification.
The mapping between generic constants and the actual values they receive when an entity is used in a component instantiation.
Corresponds directly to gate level primitives such as AND and OR.
A definition that specifies values that can be accessed through the attributes of a terminal.
An named entity that has a value of a specified type. An object can be a constant, signal, variable, quantity, terminal, or file.
Used to organize data and subprograms in a model.
A channel for dynamic communication between a block and its environment.
An interface list that declares the inputs and outputs of a block, component, or design entity. The ports can be signals, quantities, or terminals.
A mapping used in component instantiations that connects actual signals, quantities, or terminals to the formal ports defined in the port interface list for the component.
Summarizes a collection of sequential statements that are executed for their effects.
An object with a floating point value and which has a continuous solution set by the analog solver.
A quantity, used to model signal flow, that is declared in a port interface list. A direction, either in or out, must be specified on quantity ports.
A direction determined by the order of two terminals that form a branch. For a through quantity, a positive direction represents a flow from the first terminal to the second. Similarly, for an across quantity, a higher potential on the first terminal than on the second is considered a positive potential.
A terminal that is used by all terminals of a given nature as the zero for the values of its across type. Intuitively, the ground terminal for all terminals of that nature.
Systems described in the form of combinational and sequential functions such as registers, counters and decoders.
A type whose values have no elements. The integer, enumeration, physical, and floating point types.
Statements that run in sequence.
A variable that can be accessed by more than one process, and by analog expressions. The order of process execution, and therefore of access to shared variables, is unspecified within any one simulation cycle.
An object with a past history of values. Signals represent interconnection wires.
A signal, used to model signal flow, that is declared in a port interface list. Signal ports can be specified with an optional direction: in, out, inout, buffer, or linkage.
Algebraic and differential equations used to specify the analog behavior of a system.
A level of abstraction that describes a complete system.
A point of physical connection between devices. A terminal implicitly creates two quantities: T’reference (an across quantity from this terminal to the reference terminal) and T’contribution (a through quantity from this terminal to the reference terminal).
A terminal, with no direction, that is declared in a port interface list. Terminal ports are used to model conservative systems.
A quantity that represents the flow through a terminal to a second terminal.
An object with a single current value. Variables must be declared before being used in a model.
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