Glossary
A
Specifies an alternate name for a signal.
Compilation of the VHDL source code.
Describes the implementation of an entity. A single entity can have several different architectures.
Abstract syntax tree. An intermediate representation of a design produced by a VHDL analyzer.
B
VHDL expressions that describe the behavior of a component.
The assignment of specific components to specific entities. Configurations control binding.
A collection of signals with different names. A bundle is represented by names separated by a comma, for example A,B,Data<0:15>.
C
Component Description Format (CDF)
A system for dynamically changing and storing parameters and displaying information for components and sets of components for different versions (levels) of designs.
The Cadence software representation of a design element or component. It can be viewed as a collection of views that describe an individual building block of a chip or system.
The Cadence software representation of a design unit. Views can be used to delineate between design representations, such as entity, schematic, or layout. Or they can be used to specify levels of abstraction; for example, behavior, RTL, or synthesis.
Command Interpreter Window. The primary user interface for launching Cadence software. The CDF editor starts from the Tools menu in the CIW. You can enter SKILL commands in the CIW command line.
A fundamental unit within a system that encapsulates behavior and structure. Also known as an element. A cell, with cellviews and associated CDF.
Identifies the name, ports, and generics of a component. A component must be declared before it is instantiated in an architecture. The component declaration can appear within the architecture or in a package.
Describes an instance of a component contained within an architecture.
Describes how component instances are bound to design entities and how design entities are put together to form a complete design.
Binds component instances to entity architecture pairs.
A statement or basic element in a programming language.
A statement in a design unit that identifies which elements in which libraries the design unit references.
Cadence-to-Synopsys Interface.
D
The basic building blocks of a VHDL design, including entity, architecture, package, package body, and configuration declarations.
A library containing cells that describe components of a single design.
E
Binds analyzed VHDL design units into a design that can be simulated.
Describes the interface to a component. Entities communicate through generics and ports.
Values in the UNIX operating system that you set in UNIX files, such as the .cshrc file to control how the shell works.
Identifiers that begin and end with a backslash are called escaped identifiers. For example, \Name\. Unlike normal VHDL names, escaped VHDL identifiers are case sensitive. This means that the identifier \AbC\ and the identifier \aBc\ refer to two different objects. An identifier in the VHDL normal name space and the same identifier in the VHDL escaped name space do not represent the same object. For example, the VHDL identifiers abc and \abc\ refer to two different objects. To embed a backslash in an escaped identifier, use double backslashes. If the original identifier was in the VHDL escaped form even though it was legal in the VHDL normal form, it needs to be returned to the escaped form, not the normal form. For example, \abc\ maps to OA ESC_abc, and it maps back to \abc\ in VHDL. All alphanumeric characters and symbols, as well as spaces, are allowed as VHDL escaped identifiers.
F
The area on a form where you indicate values, names, and selections.
G
A constant declared in a component declaration or an entity declaration. The value of a generic can be supplied externally either in a component instantiation or in a configuration specification.
The complete and correct results of a simulation used as a measure against the success of other simulations.
I
L
An artificial intelligence language.
Language Sensitive Editor. A text editor with features specific to one programming or design language, such as syntax checking.
To make data interoperable among Cadence tools, Cadence developed a common naming convention called name mapping. When tools use data from other applications with noncompatible naming conventions, the name mapping mechanism converts the names to a recognizable language that the tool understands.
A set of rules – for example, a VHDL name space – for creating legal names that a particular tool or language uses for determining the types of identifiers and keywords that are legal for that tool.
O
P
Describes information common to multiple design units.
Describes the implementation of the declarations found in a package.
A signal declared in the interface list of an entity declaration or in the interface list of a component declaration. A port corresponds to a pin in a symbol or schematic.
Entity, package, and configuration declarations. Primary design units must be analyzed (compiled) before secondary design units.
R
A library containing cells that describes common components potentially used in many designs.
S
Architecture and package body declarations. Secondary design units must be analyzed (compiled) after primary design units.
Connections between component instances, providing for communication of dynamic data between components.
Simulation History Manager or Simulation History Management.
A proprietary Cadence high-level interactive programming language based on the artificial intelligence language, LISP.
T
Defines a set of values and a set of operations, such as bit, std_logic, or integer.
V
See
Very High Speed Integrated Circuit.
VHSIC Hardware Description Language.
W
The library where the result from analyzing a VHDL design unit is placed. There can be only one working library.
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