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Contents

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1

About the VHDL Integration Environment

Licensing Requirements

Schematic Design Process Flow

Updating a Design

Netlisting the Design

Specifying a Testbench

Simulating the Design

VHDL Integration Environment Tools

VHDL Toolbox Window

Simulation Window

SimCompare Tool

Managing the Run Directory

How Data is Organized

Design Library Storage

VHDL Design Units

Design Views

VHDL Name Mapping

VHDL Text View Database

Netlist and Simulate a VHDL Design

Using the Command-Line Interface

Using the Graphical User Interface

2

Introducing the VHDL Toolbox

VHDL Toolbox Features

Opening the VHDL Toolbox GUI

VHDL Toolbox GUI

Run Directory Group Box

Top Level Design Group Box

Menu Bar

Status Line

Fixed Menu

Command Buttons

Exiting the VHDL Toolbox

3

Netlisting a VHDL Design

Initializing the Run Directory

Configuring the VHDL Netlister

Customizing Pre- and Post-Processing Functions

Setting up Hierarchical Specifications

Setting up the VHDL Netlister for Inherited Connections

Additional Features of the Netlister

Generating the Netlist

Viewing Netlist Results

Analyzing the Netlist

4

Creating a Testbench

VHDL Create Test Bench Form

Methods to Create a Testbench

Automatic Generation of Testbench

Providing an Existing Testbench

SKILL Variables to Configure Testbench Creation

5

Simulating a Netlisted VHDL Design

Simulating a Design Using the VHDL Toolbox

VHDL Setup - Simulation Form

Simulating the VHDL Design

Debugging Your VHDL Design

Editing from the XM-VHDL Simulator

Using Cross Selection

Comparing Simulations

VHDL Setup - Sim Comparison Form

Comparing VHDL Simulations

Simulating a VHDL Design Using Non-Cadence VHDL Tools

Parser CallBack

Analyzer CallBack

Analyzed File String

Elaborator CallBack

Simulator CallBack

Data Directory CallBack

Data File CallBack

Work Library CallBack

6

Modeling Schematics as VHDL

Mapping Case Sensitivity

Mapping Library, Cell, and Cellview Names to VHDL

Mapping Identifier Names to VHDL

Matching Compliant and Noncompliant Data

Assigning VHDL Data Types

Modeling Schematic Pins as VHDL Ports

Supporting Port Bundles

Discontinuous Ports

Modeling Schematic Nets as VHDL Signals

Supporting Global Signals

Aliasing Ports and Signals

Modeling Feedback Signals

Signal/Port Name Collisions

Modeling Schematic Instances as VHDL Instances

Ignoring Instances

Modeling Iterated Instances

Modeling Instance Properties as Generics

Specifying Explicit Component Binding

Specifying Components Declared in External Packages

Modeling Multisheet Schematics

7

Customizing Your Environment

Setting VHDL HNL Variables

Setting VHDL CDSENV Variables

Setting xrun Variables

8

VHDL Netlister Properties

9

Running Simulations with Xcelium

Glossary

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