Known Problems and Solutions in SystemVerilog Integration Environment

This document describes the known issues with Virtuoso^® Verilog Environment for SystemVerilog Integration (SystemVerilog Integration Environment) and suggests the workarounds for these issues. Each issue is identified by a Cadence Change Request (CCR) number.

Related Topics

Introducing SystemVerilog Integration Environment

CCR 1104924: Simulation settings do not update when you switch between the NC Verilog Environment and the SystemVerilog Integration Environment

Description: The simulation settings for NC Verilog Environment do not update when you perform the following steps.

1. Start a Virtuoso session.
2. Use the SystemVerilog Integration Environment.
   Launch the environment for a design and initialize the run directory. You can also customize settings and netlist the design.
3. Exit the SystemVerilog Integration Environment.
4. Launch the NC Verilog Environment.

In this case, the NC Verilog Environment fails to netlist a design because the simulation settings, including view lists, do not update.

Similarly, when you first use the NC Verilog Environment in a session and then use the SystemVerilog Integration Environment, the simulation settings do not update.

Solution: Ensure that the flag vlogifVicSimSimulator is not set in your run directory and start a new Virtuoso session. Then use the SystemVerilog Integration Environment or the NC Verilog Environment.