Known Problems and Solutions in VHDL In
This document describes the known issues with VHDL In and suggests the workarounds for these issues. Each issue is identified by a Cadence Change Request (CCR) number.
Related Topics
CCR 483839: CDS_INST_DIR works as a reserved variable for vhdlin
Description: The CDS_INST_DIR is an environment variable that is evaluated to cds_root verilog while running VHDL Import.
Solution: Use a variable name other than CDS_INST_DIR in the cds.lib file.
CCR 483244: VHDL design having generate statement is imported as text instead of schematic
Description: VHPL APIs do not provide details of generate constructs while using the ncvhdl parser, therefore if a VHDL design has generate constructs, the design is imported as text instead of schematic.
Solution: This is a known issue and currently no solution is provided for this.
CCR 448134: VHDL In will not be able to import configuration bindings
Description: If there are VHDL configurations in VHDL design to be imported, the binding information is available in the generated schematic.
Solution: This is a known issue and currently no solution is provided for this.
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