1 Introducing SystemVerilog Integration Environment

Virtuoso^® Verilog Environment for SystemVerilog Integration (SystemVerilog Integration Environment) is an environment for generating netlists of SystemVerilog-based digital designs. This environment also integrates with other Cadence tools to simulate and debug designs.

This topic describes how to use the Virtuoso^® Verilog^® Environment for SystemVerilog Integration (SystemVerilog Integration Environment) to netlist and simulate SystemVerilog-based designs.

This topic is aimed at developers and designers of integrated circuits and assumes that you are familiar with:

The Virtuoso Studio design environment and application infrastructure mechanisms designed to support consistent operations between all Cadence^® tools.
The applications used to design and develop integrated circuits in the Virtuoso Studio design environment, notably, the Virtuoso Layout Suite, and Virtuoso Schematic Editor.
The Virtuoso Studio design environment technology file.
Component description format (CDF), which lets you create and describe your own components for use with Layout XL.

This document includes the following topics.

Licensing Requirements

SystemVerilog Integration Environment requires the following licenses:

Virtuoso Schematic Editor XL license (License Number 95115)
Virtuoso Schematic Editor Verilog Interface license (License Number 21400)

For information about licensing in the Virtuoso Studio design environment, see Virtuoso Software Licensing and Configuration Guide.

Key Features

SystemVerilog Integration Environment provides a methodology to netlist and simulate SystemVerilog-based designs. This methodology includes the following stages:

Initialize the run directory for storing the netlist and simulation data.
Generate the netlist of the design that describes the connectivity of the design.
Simulate the design using the generated netlist as an input.

SystemVerilog Integration Environment provides the following key features and capabilities:

A graphical user interface and a command line interface
Various options for configuring netlist generation and design simulation
Support for various SystemVerilog data types, such as release interface, custom, wire, reg, logic, string, and event
Data type progression from leaf-level SystemVerilog cellviews to top-level schematic design hierarchy, and an option to override the progression
Netlist generation for configuration and non-configuration based designs
Netlist generation and simulation of mixed-language design where Verilog and SystemVerilog views coexist at the leaf level
Support for handling packed and unpacked arrays in the design during netlist generation
Awareness of the following file extensions:
- SystemVerilog file extensions .sv,.SV,.svp,.SVP,.svi,.svh,.vlib,.VLIB
- Verilog file extensions .v, .V, .vp, .VP, .vs, and .VS
- Other user-specified Verilog and SystemVerilog file extensions
Design simulation in the following modes:
- Interactive mode that lets you choose the compilation, elaboration, and simulation steps to perform
- Batch mode that performs all steps
Integration with Cadence^® SimVision to let you simulate and debug designs in interactive mode

The Cadence^® SimVision is a simulation analysis environment for debugging digital, analog, or mixed-signal designs written in Verilog, SystemVerilog, VHDL, SystemC, or a combination of those languages. For more information, see the SimVision User Guide.

Netlist Generation and Design Simulation Flow

The following figure illustrates the flow through which SystemVerilog Integration Environment generates a netlist of a design and simulates that design.

The generic steps for using SystemVerilog Integration Environment are as follows:

Create your design. The design can have Verilog and SystemVerilog cellviews coexisting at the leaf level.
Virtuoso lets you create a SystemVerilog text-only cellview and a symbol for it, which you can integrate in your design. For details, see “About Creating SystemVerilog-Based Designs”.
Open the top cellview of the design in Virtuoso Schematic Editor L or XL and launch SystemVerilog Integration Environment. You can open the schematic view or the configuration view of the design.
For details, see “Launching the Graphical User Interface”.
Initialize the run directory for netlist generation and design simulation.
For details, see “Initializing the Run Directory”.
Set options for netlist generation and generate the netlist of the design.
SystemVerilog Integration Environment also creates a map file containing:
- The netlist configuration options.
- Map of the names used in the netlist and their corresponding name in the design.
You can view contents of the netlist and the map file.
For details, see “Netlisting a Design”.
Set options for simulating the design. You can also set the testbench and stimulus. Then choose the batch or interactive mode and start the simulation.
If you choose the interactive mode, SystemVerilog Integration Environment launches SimVision to simulate the design after the design compilation and elaboration is complete.
If you choose the batch mode, the environment simulates the design in the background. The environment provides a window to monitor the status of design simulation in the batch mode.
For details, see “Simulating a Design”.
Analyze simulation results as required.

If you encounter issues using SystemVerilog Integration Environment, refer to the log that the environment displays in the Virtuoso CIW. It also displays the status of the last operation on the main form.

Tool Requirements

You launch SystemVerilog Integration Environment from the Virtuoso Schematic Editor L or XL.

To perform its operations, SystemVerilog Integration Environment requires the following tools:

Cadence xrun utility
The xrun utility is used to simulate a design. It specifies all the input files and options in a single command line.
The xrun utility can take SystemVerilog and Verilog files as inputs. The utility uses the Native Code tools to compile, elaborate, and simulate the design.
The executable and log file names will depend on the simulator being used. For the changes in the executable and log file names when using the Xcelium simulator, see Running Simulations with Xcelium
Cadence Native Code (NC) tools
The xrun utility uses the following NC tools to simulate designs:
- Native Code Compiler (xmvlog) compiles SystemVerilog and Verilog-based designs.
- Native Code Elaborator (xmelab) gathers various portions of a design and creates a snapshot for simulation.
- Native Code Simulator (xmsim) simulates the design in the batch mode.
  The xrun utility uses the input filename extension to determine the compiler it should use to compile the input files. To compile SystemVerilog files, the utility runs xmvlog with the -sv option.
Cadence SimVision
SimVision provides an environment for simulating and debugging digital designs written in SystemVerilog or a mix of Verilog and SystemVerilog languages. SystemVerilog Integration Environment launches this tool after design compilation and elaboration is completed in the interactive mode.

Graphical User Interface

You can use SystemVerilog Integration Environment from its graphical user interface and command line interface.

This section provides information on the following topics:

For information on the command line interface, see “Using Standalone Mode”.

SystemVerilog Integration Environment and the Virtuoso^® Verilog Environment for NC-Verilog Integration have a similar user interface.

Launching the Graphical User Interface

To launch the graphical user interface of SystemVerilog Integration Environment:

Open the top cell of your SystemVerilog-based design in Virtuoso Schematic Editor L or XL. You can open the top cell using the schematic view or the configuration view.
Choose Launch — Plugins — Simulation — SystemVerilog. The main form of SystemVerilog Integration Environment appears.

Understanding the Graphical User Interface

The following figure illustrates the main form of SystemVerilog Integration Environment.

The following table describes the main form components.

Component	Description
Menu bar	Access the following menus to perform various operations. Commands: Access options to initialize the run directory, generate the netlist, specify the testbench and stimulus, and simulate the design. Setup: Access the forms for setting netlist generation options and simulation options. Results: Access options to view the netlist and map. Also access the job monitoring window to view the batch simulation status. Help: Access help on using SystemVerilog Integration Environment.
Toolbar	Click the following shortcut toolbar option to perform tasks. Initialize Design: Initialize the run directory for netlist generation and design simulation. Generate Netlist: Generate a hierarchical netlist of the design in the run directory using the netlist generation settings. This option becomes available after you initialize the run directory. Simulate: Simulates the design in interactive or batch mode using the simulation settings. This option becomes available after you generate a netlist of the design.
Status message	Shows the status of the last operation. The status can be: `Uninitialized`: The run directory must be initialized before you can netlist and simulate the design. `Ready`: The run directory has been initialized and you can start generating the netlist. `Netlisting Succeeded`: The netlist has been generated and you can start simulating the design. `Compiling Design`: Design compilation is in progress. `Compilation Successful`: The design files have been compiled. `Elaborating Design`: Design elaboration is in progress. `Elaboration Successful`: The design has been elaborated and you can start the simulation. `SimVision Launched`: SystemVerilog Integration Environment has launched SimVision for interactive design simulation. `Batch Simulation`: SystemVerilog Integration Environment is simulating or has simulated the design in the batch mode using the xmsim tool.
Run directory	Specify the run directory for storing the netlist, simulation, and waveform data. For details, see “Initializing the Run Directory”.
Design details	Specify the library, cell, and view of the top-level design. By default, the environment displays the library, cell, and view of the design opened in Virtuoso Schematic Editor, from where you launched the environment. You can change this design reference. For details, see “Initializing the Run Directory”.
Simulation mode options	Specify the simulation mode. You can select Interactive or Batch mode of simulation. For details, see “Simulating a Design”.
Help text	Displays help tips on the selected user-interface component.

About Creating SystemVerilog-Based Designs

Virtuoso lets you create a SystemVerilog text-only cellview and a symbol for this cellview, which you can use in your SystemVerilog-based design. You can create and manage your design using the Virtuoso Schematic Editor, and netlist and simulate this design using SystemVerilog Integration Environment.

For information on working with designs, see the Virtuoso Schematic Editor L User Guide.

Virtuoso provides support for handling packed and unpacked arrays during SystemVerilog symbol generation.

You can create a SystemVerilog cellview and its symbol using the procedure described below. You can import text cellviews from Verilog, SystemVerilog, Verilog-AMS, VHDL, and VHDL-AMS text files into the DFII environment using the cdsTextTo5x command. This command also lets you generate the symbol views of the imported cellviews. For details, see Importing Design Data by Using cdsTextTo5x. You can also use this command to create text cellviews (5x structure), symbol views, and shadow database for SPICE, Spectre, DSPF, and PSpice.

You can also generate the text database for a given cellview without opening the Text Editor, using the hdlGenerateTextDatabase SKILL function:

To create a SystemVerilog cellview and symbol:

Choose File — New — Cellview from the Virtuoso menu. The New File form appears.

Specify the cellview details.

Field	Details
Library	Select the library to which you want to add the new cell.
Cell	Enter the name of the new cell.
View	Specify the default view as required. If you leave this field blank and select a view type from the Type list, the field automatically displays the default view of the selected type,
Type	Select `systemVerilogText` from the list of view types. If the View field is blank, it updates to display `systemVerilog`.
Open with	Select the default Text Editor.

Click OK.
Virtuoso creates a blank SystemVerilog cellview and stores it as LibraryName/cellName/viewName/verilog.sv. It also displays this file in Virtuoso Text Editor.
Add your SystemVerilog cellview code and save the file.
Virtuoso parses the file. It prompts you to correct any syntax errors in the file.
The following figure illustrates an example of a SystemVerilog cell.

After parsing the file that does not have any syntax errors, Virtuoso prompts you to save its symbol.
Click Yes on the prompt to save the symbol of the new cell.

Virtuoso CIW displays logs to indicate the status of the SystemVerilog cellview and symbol creation. Following are example logs:

Cellview can_counter symbol does not exist.

Symbol (can_counter symbol) generated and saved in library:demo_lib.

Processing Completed

  errors:0, warnings:0

To open the new cellview or symbol for verification:

Choose File — Open from the Virtuoso menu. The Open File form appears.
Select the library, cell, and view of the new cellview file. You can choose to view the symbol or the SystemVerilog text-only view.
Click OK. You can verify the text-only SystemVerilog view or symbol. See the following figure.

To create a SystemVerilog package view:

Choose File — New — Cellview from the Virtuoso menu. The New File form appears.

Specify the package view details.

Field	Details
Library	Select the library to which you want to add the new package.
Cell	Enter the name of the new package.
View	Specify the default view as required. If you leave this field blank and select a view type from the Type list, the field automatically displays the default view of the selected type,
Type	Select `systemVerilogPackageText` from the list of view types. If the View field is blank, it updates to display `systemVerilogPackage`.
Open with	Select the default Text Editor.

Click OK.
Virtuoso creates a blank SystemVerilog cellview and stores it as LibraryName/cellName/viewName/package.sv. It also displays this file in Virtuoso Text Editor.
Add your SystemVerilog package view code and close the file.
Virtuoso parses the file. It prompts you to correct any syntax errors in the file.

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Virtuoso Verilog Environment for SystemVerilog Integration User GuideProduct Version IC23.1, June 2023

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Introducing SystemVerilog Integration Environment