Known Problems and Solutions in Virtuoso Electrically Aware Design Flow
This document describes the known issues with the Virtuoso® Electrically Aware Design Flow and suggests the workarounds for these issues. Each issue is identified by a Cadence Change Request (CCR) number.
Related Topics
CCR 1813295: Missing or incomplete layer mappings in the process setup (.ini) file affects high precision C extraction
Description: When a conformal dielectric layer is expanded from sub_conductor layers that are either unmapped or mapped incorrectly in EAD process.ini file, Layout EAD fails to complete high precision C extraction, and Virtuoso may stop responding or close abruptly.
Solution: Ensure that all conductor and sub_conductor layers have correct layer mappings.
CCR 1631710: The Automatically zoom display to selected network or parasitic command in the EAD Browser of VSE XL does not work properly in all cases
Description: When using EAD Browser in VSE XL, the Automatically zoom display to selected network or parasitic command on the toolbar does not work properly for all the nets. At times, it zooms to only a part of the selected net or none of the net.
Solution: Currently, a workaround is not available. You can manually zoom to a net or use the Zoom to Selected command from the View menu of the Virtuoso Schematic Editor XL window.
CCR 1631699: When you display capacitance annotations for the top level schematic in Virtuoso Schematic Editor XL, EAD fails to determine capacitance for internal nets
Description: When you use the Annotate All Nets Total Cap command on the EAD Browser assistant in VSE XL to display annotations for top level schematic, EAD fails to determine capacitance for internal nets, and displays warning messages in CIW.
Solution: Currently, a workaround is not available. You can view the total capacitance value for a net in the summary table of the EAD Browser.
CCR 1557857: The commands on the EAD toolbar are active even if the setup is not loaded in the EAD Browser
Description: The commands on the EAD toolbar are active even if the setup is not loaded in the EAD Browser. However, if used, they do not have any effect.
Solution: Currently, a workaround is not available.
CCR 1409768: If the -lsf_number option is not specified with -lsf_command, the eadModelGen command is run on the local computer
Description: If you specify the -lsf_command option with the eadModelGen command to run the model generation jobs using LSF, but do not specify the -lsf_number option, the jobs are not sent to the LSF resource. Instead, they are run on the local computer.
Solution: Ensure that when the -lsf_command option is used, you also set the -lsf_number option to a value greater than 1.
CCR 1123547: Resistance and Current Limit are displayed on dynamic display but not on info balloon
Description: During wire editing, a virtual node is created at the end of the newly-created wire in order to force the extractor to add a resistor that represents the wire while it is being drawn. After the wire has been created, if the wire is dangling, the virtual node is deleted, which means that no resistor is extracted for it, and no resistance or current limits are computed for it.
Solution: For information only.
CCR 1107646: Extracting shapes with diagonal edges at angles other than 45 degrees results in lower resistance than expected
Description: If your layout design contains shapes with diagonal edges at any angle other than 45 degrees, Layout EAD might approximate the width incorrectly resulting in lower resistance values than expected.
Solution: Use only shapes with orthogonal or 45-degree diagonal edges when designing the physical layout.
CCR 1106601: Resimulation fails when flattening the schematic that contains mutual inductors
Description: In the resimulation flow, the DUT hierarchy is flattened to stitch the layout parasitics correctly. If the DUT contains mutual inductors, these are also flattened, but the parameters pointing to the inductors are not updated. This leads to a simulation failure because the inductors cannot be found.
Solution: For the components that contain inductors and mutual inductors, copy the symbol view to a view named noflatten and set the following two variables in the .cdsenv file:
envSetVal("msps" "switchViewList" 'string "noflatten spectre schematic veriloga")
envSetVal("msps" "stopViewList" 'string "noflatten spectre veriloga")
These variable settings inhibit the flattening of these components and the simulation runs successfully.
CCR 1105082: Point-To-Point Info Balloon is disabled when EM checking is disabled
Description: The Point-To-Point Info Balloon feature lets you visualize parasitic effects and EM violations between two user-specified points on a net, however, this feature is disabled when EM checking is disabled.
Solution: Enable EM checking from the EAD Browser assistant to use the Point-To-Point Info Balloon feature.
CCR 1072869: EAD crashes when loading a dataset stored in "psf with floats" format
Description: If you try to load a dataset where the currents were stored in "psf with floats" format, VLS EAD crashes.
Solution: Do not use "psf with floats" format in your datasets. Use the "psf" and "psfxl" formats, which are more suited for this purpose.
CCR 1039804: The EAD Browser’s "Select Partial Network" feature does not support standardVias
Description: When using Select Partial Network mode, selecting standardVias in the canvas does not display information for the vias in the EAD Browser.
Solution: Select the wires around the vias to see information about the vias in the EAD Browser.
CCR 922947: The Point list in the EAD Results view does not contain the ALL option
Description: The Point list in the EAD Results View does not contain the ALL option. As a result, you cannot create a dataset that includes the results for all the data points.
Solution: Create a separate dataset for each simulation point.
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