Figure 1-5 The Smart View after resistance, capacitance, and inductance parasitics are displayed

To change the style of inductance annotation, set the svInductorStyle environment variable to ROUND or SHARP.

You can annotate the inductance with or without the resistors connected in series by toggling the Resistance option in the Display Parasitics form.

By default, the Smart View does not display the names of net fragments for parasitic nodes. To display these names, select the Node Name option in the Display Parasitics form or set the svDisplayNodeName environment variable to t. Alternatively, select a square on the parasitic display and choose Parasitics – Probe Node

The size of the parastic nodes might be small, especially in case of complex technologies. In such cases, you can use the svDotWidth environment variable to control the display size of the parasitic nodes.

If the Smart View has been generated without any layer information, a Y3:drawing layer is created for the parasitic nodes. This ensures that the nets can be selected directly on the parasitic display or using the Direct Plot command, and then added to the ADE outputs.

Smart-Parasitics – Clear Parasitics

Select Smart-Parasitics – Clear Parasitics to remove the parasitics that are displayed by the Display Parasitics form.

Smart-Parasitics – Overlay Layout

Select Smart-Parasitics – Overlay Layout to display the corresponding layout view in the background while keeping the Smart View in the foreground. The background layout view is displayed in a new adjacent tab.

The following illustration shows a Smart View design with the parasitics displayed by selecting Smart-Parasitics – Display Parasitics.

Figure 1-6 The Smart View before the layout is overlaid

Selecting Smart-Parasitics – Overlay Layout displays the following view:

Figure 1-7 The Smart View after layout is overlaid

Accessing Smart View in ADE

Parasitic aware design allows you to access the Smart View feature in the ADE flow. You can display and probe parasitics, generate reports and make comparisons between the parasitic elements in the Smart View.

The typical flow to use the Smart View in ADE is as follows:

1. Create the Smart View using Quantus.

1. Open a maestro cellview in ADE Assembler.
   
   The design block in the schematic for this cellview should be bound to the Smart View. This can be a view or a configuration that is bound to the Smart View.
2. Run the simulation in your ADE Assembler setup. When the simulation run completes you can select outputs and probe the design on the schematic.

1. In ADE Assembler – Parasitics/LDE – Setup form, select the Smart View in the Extracted tab.
2. Select the output on the Results tab.
3. Right-click and choose Direct Plot to descend into the Smart View to probe nodes directly in the parasitic display. See In-Context Probing.

Using the Smart View with ADE, you can analyze the extracted parasitics and their extraction results and determine the cause of unexpected outputs.

Accessing Parasitic Aware Design Functionality in ADE Explorer, ADE Assembler and Schematics L/XL

You can access parasitic aware design functionality if the current view is:

• a schematic view
• an extracted view
  
  Virtuoso Parasitic Aware Design supports simulation cross-probing of schematic nets even when the extracted view is used in the simulation.
• a Smart View
• a configuration view (the schematic can refer back to a configuration).

To access Parasitics from Schematics L/XL:

• Select Launch – Plugins – Parasitics from the Schematics L/XL menu bar.
  This will add a Parasitics Menu to the Schematics L/XL menu bar.
  
  The Parasitics menu is displayed by default when you are working with ADE Explorer or ADE Assembler.

Parasitics Menu

Selecting Launch – Plugins – Parasitics adds a Parasitics menu to Schematics L/XL with the following menu options:

Figure 1-8 The Parasitic menu items

A summary of the Parasitics menu options in Schematics L/XL is detailed below:

• Parasitics – Set Up requires that you complete the necessary schematic, extracted, or configuration details before proceeding with parasitic aware design.
  
  Along with the Parasitics – Options menu-item, Parasitics – Set Up is the only menu-item initially enabled.
• Parasitics – Options displays the Options form whose value settings determine how parasitic aware design handles certain backannotation and parasitic probing tasks.
• Parasitics – Parametric Variables displays the Specify Parameters Values form which can be used to set and edit parametric values for use in parasitic simulation.
• Parasitics – Show/Hide Parasitics lets you choose to turn on or off the display of parasitic values in the current schematic view. This in turn controls parasitic backannotation.
• Parasitics – Report Parasitics lets you undertake parasitic reporting on a selection of nets and terminals.
• Parasitics – Refine Extracted View can be used to generate a refined extracted view that can be used for circuit simulation.
• Parasitics – Probe Design Inst/Net can be selected to probe a design instance or net, from the current schematic view, to extracted instances in the extracted view, or vice versa.

Parasitics – Set Up

When parasitic aware design is enabled only the Set Up and Options menu options are available.

• If you access Parasitics – Setup from a schematic or extracted cellview you will have to complete the required Schematic Cellview or Extracted Cellview sections in the Setup form before you can continue to use parasitic aware design functionality (see Parasitics Set Up for Schematic and Extracted Views).
• If you access Parasitics – Setup from a top level configuration, or after you descend into a sub-block of the configuration, you will have to complete the required Config Cellview or Simulation Data sections in the Setup form before you can continue to use parasitic aware design functionality (see Parasitics Set Up for Configuration Views).

Selecting Cellviews to use with Parasitic Aware Design

You will not be able to proceed with parasitic functionality until either the schematic and extracted cellviews have been entered correctly, or a configuration view and simulation results have been chosen.

You can specify a cellview to use as follows:

• By clicking on the Browse button on the Parasitics Setup form and locating the view in the Library Browser form.
• By choosing the Select by Cursor option and then clicking on the relevant view.
• By selecting the view from the appropriate form fields.

Initial Parasitic Setup

Parasitic setup can take one of three forms dependent upon the following scenarios:

1. If you open a schematic view you will be displayed with a version of the Setup Parasitics Form (Figure 1-9) that asks for extracted view details.
   If you open a configuration you are asked for a simulation database (Figure 1-10).
   
   The decision as to which Parasitics Setup form is displayed is dependent upon what cellview type is current.
2. If a schematic in the design below the top-level view has been opened directly, just knowing the top-level view, or configuration, is not enough to determine which extracted view or Smart View (if any) corresponds to that schematic.
   This is because the schematic cannot be associated with a hierarchical instance path. In this scenario, you must specifically select the extracted view.
   However, as there is a risk that you may inadvertently select an extracted view that has not been simulated, the annotation of resistance (R) (Effective R Calculations) values will be disabled to avoid annotating incorrect effective values for the selected extracted view.
3. You have an extracted view open, in which case you must specify a matching schematic.

If required, you can change the Setup Parasitics form options at any time, with any changes made to the form being recorded for future use.

Parasitics Set Up for Schematic and Extracted Views

The Setup Parasitics form below will appear if you access parasitic aware design functionality from a schematic or extracted cellview.

Figure 1-9 The Setup Parasitics form for schematic and extracted cellviews

Parasitics Set Up for Configuration Views

If you select Parasitics – Setup from a configuration view you are requested to enter database information.

If you have opened a schematic via a simulation configuration you will not need to specify either view as this will information will be derived when you perform Out-Of-Context Probing.

Figure 1-10 The Setup Parasitics Form (for configuration cellview in Schematics L/XL)

Parasitics – Options

The parasitic aware design Options form contains a range of options related to Backannotation and Parasitic Probing Reports.

Figure 1-11 The Options Form

Parasitics – Parametric Variables

The Specify Parametric Values form can be used to set and edit parametric values specified on parasitic instances for use in parasitic simulation.

Quantus QRC extraction controls the specification of parametric variables, which are the result of using Multiple Rule Sets to run extraction on different process corners. For more information on this see Use Multiple Rule Sets in the Quantus QRC Graphical User Interface section of the Quantus QRC Extraction Users Manual.

An example of parametric C:

C
 = Cmin * iPar("c-min") + Cmax * iPar("c-max")

To set parametric variables:

1. Select Parasitics – Parametric Variables.
   The Specify Parametric Values form is displayed.
2. Select the Library Name and Cell Name whose variables you want to set (you can use the Browse button to invoke the Library Browser to assist this, or use the Select By Cursor button to select directly from the design canvas).
   
   Cell Name must be the Analog Design Environment (ADE) cellview where the variables were originally set.
   For information on how parametric variables are set and edited in ADE, see Design Variables and Simulation Files for Direct Simulation in the Virtuoso ADE Explorer User Guide .
   You can also click the Load Values button to load parametric variable values that were set in the Edit Design Variables form in ADE. Here, you should select Variables – Copy To Cellview in ADE before choosing to load these values in.
3. Optionally, edit the values of variable to suit your requirements then choose Apply or OK.
   To save changes to parametric values for use in ADE select Save Values. Once these edits have been applied you can load the new values back into ADE by selecting Variables – Copy From Cellview in ADE.
4. Click OK to apply the new parametric variable values and close the Specify Parametric Variables form.

Parasitics – Show/Hide Parasitics

You can choose to turn on or off the display of generated parasitic values in the current schematic view.

If you show/hide parasitics on a particular schematic (which, as mentioned, must be defined in the schematic hierarchy in the Schematic Cellview section of the Parasitics – Set Up form), and descend/ascend the hierarchy, the state will be remembered so that in the new level parasitics will continue to be displayed as in the previous level.

Figure 1-12 The display of parasitic values turned on

The use and operation of Show/Hide Parasitics is discussed further in Performing Backannotation.

Parasitics – Report Parasitics

The following parasitic probing report options are available under the Report Parasitics menu option:

• Reporting on Nets (Net and Net to Net)
• Reporting on Terminal to Terminal
• Reporting on Net Capacitors
• Reporting on All Nets
  
  
  Figure 1-13 Available Parasitic menu reports

Sum Totals

Any sum Totals at the bottom of a report displays the effective and summed values (C, L, and K will always be summed, while R depends on the type of probing) for each parasitic type that has been found for the particular type of probing.

For example, even if you filter out R or C by deselecting their respective options at the top of the Parasitics Report form, the summary totals will still remain the same. If available, effective totals will also be displayed (these will not be available if a DC op point simulation has not been run).

For information on running a DC simulation, see Preparing for Resistance Backannotation (Running a DC Analysis).

Reported Values

Parasitic aware design uses the aelSuffixNotation function to print the values of capacitance and resistance, with 4 as the default number of digits set to be displayed.

It is possible to view rounded values in a report form rather than the value that is displayed on the extracted view.

For example, you may see r = 143.1453m on the extracted view but in the parasitics report the 4 digit setting would display r = 143.1m.

You can however change the number of digits displayed. For example, to get full precision you should set:

aelPushSignifDigits (15)

Sorting the Report Table

Parasitic report tables can be sorted by clicking on the desired column option header.

The default sorting method is specified using the Initially Sort By option in the Parasitics – Options form.

Saving Report Data

You can save the contents of a report table, for example, a parasitic report or an instance probing report, to a specified report file by clicking on the Save button at the bottom of the applicable form.

The save action will record the information as per any sort and filter specifications you have already made.

You also have the option to save the information as either a Text file (.txt), or a Comma separated value file (.csv). If you want to change the name of the report you can edit the Filename as required.

Figure 1-14 Saving report information

Reporting on Nets

If you choose to report on a Net or on a Net to Net basis, this will invoke the following Parasitic report form (Figure 1-15 or Figure 1-16).

The title bar of the Parasitic report displays the net location in a hierarchical format, for example: Parasitics for net /gnd! or Parasitics from net /gnd! to net /compout.

Before the Parasitics report form is displayed you will be prompted to select the appropriate net/nets that you want to report on.

Figure 1-15 Parasitic report for net /IN

Figure 1-16 Parasitic report for parasitics from net /gnd! to net /net17

The content of the Parasitics nets report forms can be specified in the Display section at the top of the report.

The columns displayed in the Parasitics nets report forms are related to:

Reporting on Terminal to Terminal

Using the terminal to terminal probing, you can report parasitics between two instance terminals or between a terminal and a pin on the same net.

The Parasitic Report assistant will report parasitics between the two most recent selections only. If multiple selections are done, all terminals or pins other than the last two selected will be ignored. Other object type selections are also ignored.

The format displayed in the title bar of the Terminal to Terminal Parasitics report is:

from (terminal|net) (<schTerm>(<extNets>+))+ to (terminal|net) (<schTerm>(<extNets>+))+

Here, the term net is used instead of terminal when a selection is taken from an extracted view, as only extracted nets would be available.

Also, (<schTerm>(<extNets>+))will be replaced by <bus_name> if you select All when you have a list of buses.

When performing a terminal to terminal probe or generating report (also known as a point-to-point probe), where two selected terminals map completely to the same extracted nets, a warning describing the situation will be issued. The resultant report will also reveal that no parasitics have been found between these terminals. This happens because the terminals are considered to be shorted, and parasitics will therefore have no influence on the interaction between the two terminals in question.

However, if you subsequently perform a whole net probe on the same net, parasitics could still be reported, even if the net is a two terminal only net.

For example, if you consider two mFactored transistors (mFactor = 2) T1 and T2, with the source of T1 connected to the drain of T2. Selecting T1-source and T2-drain, in the schematic, will identify that T1_m1-source is shorted with T2_m1-drain and T1_m2-source shorted with T2_m2-drain. As mentioned, terminal to terminal probing would complete, reporting no parasitics, however whole net probing will identify and report any parasitics that might exist between T1_m1-source and T2_m2-drain.

Selecting Leaf Terminals

The Select leaf terminals form is displayed when you perform terminal to terminal probing and select hierarchical terminals that have more than one leaf terminal.

From the Select leaf terminals form, you must select the terminals (for example, gate and drain) that you want to measure resistance values for.

Selecting individual terminals will prevent the results of net point probing (that has parallel resistors) being reported as a sum of the resistance values.

Reporting on Net Capacitors

To create a net capacitors report select Parasitics – Report Parasitics – Net Capacitors, and then select the net you want to report on.

Reporting on net capacitors generates the Capacitors for net report which displays summed capacitances (Sum C) between the selected net and all nets that it is connected to via parasitic capacitors.

Figure 1-17 Capacitors report for net /vdd!

Reporting on All Nets

Reporting on all nets generates the All Parasitics design report form.

Figure 1-18 All parasitics report for TOP design

The All Parasitics report lists each net in the design along with the total value for the net based on either the effective value or the summed value.

The decoupled C, coupled C, and coupled self C check boxes control what capacitors are summed for the sum C column.

You can also save the All Parasitics report information to a file using the Save button with the option to save the information in either text (.txt) or comma separated (.csv) format.

Parasitics – Refine Extracted View

Selecting the Parasitics – Refine Extracted View menu option will display the Refine Extracted View form with the name of the current extracted view in the title bar.

Figure 1-19 Refine Extracted View form with current view in title bar

The purpose of this option is to generate a refined extracted view that can be used for circuit simulation. The refined extracted view is based on the full extracted view created in Quantus QRC.

After the refine extracted view has been created, a window is displayed summarizing the parasitics in the new view. This information is also output to the CIW.

For more information on this process, see Step 3: Building a Refined (Analog) Extracted View Using Parasitic Aware Design.

Within this form, you can specify the extracted parasitics required for the extraction.

The refine extracted view will not remove any resistance that is associated with inductors as long as the inductors are not filtered out. This will prevent the creation of zero-resistance loops in the refined parasitic net.

Parasitics – Probe Design Inst/Net

Select Parasitics – Probe Design Inst/Net to:

• probe from a design instance or net in the current schematic view to extracted instances in the extracted view. The probe performed will raise the Extracted insts associated with... form (see Figure 1-20) from where you can pan and zoom to selected instances.
  or
• probe from a design instance or net in the extracted view to the schematic view. The probe performed will highlight, but not zoom in on, the schematic instance. If the schematic instance is within a hierarchical block in an open schematic then the block will be highlighted.
  
  When probing from the extracted view highlighting in the schematic view will only work when the schematic is open in its own right. It will not work when the schematic is open through a config.

If attempting to probe from hierarchical blocks/instances a warning message will be displayed in the CIW. To resolve this, you must descend the hierarchy (Edit – Hierarchy – Descend...) and probe at the leaf level.

If you are probing a schematic net that exits the current hierarchy level the probe will be restricted to the instances attached to that net in the current level and not the full design. Probing therefore remains localized.

After you have selected a regular device (instance or net) to probe, the relevant Extracted/Schematic insts associated... form is displayed.

This tabular form lists all of the Extracted/Schematic inst names, and their associated Type, that are related to the device that you selected. The results are viewed in sortable columns.

Figure 1-20 Extracted instances report form

For a design net, the displayed list contains all of the extracted or schematic instances that are attached to that net in the other view type.

If you select one or more extracted instances from the list (using the Control/Shift keys), this causes the extracted view to automatically zoom into those instances, highlighting the selected items in both the schematic and extracted views.

If performing a multiple factor (m-factor) selection, it is generally the case that the instances will be found, and highlighted in the same area of the chip. An m-factor device is where a single cell instance represents multiple instances of a parallel connected cell.

Clicking on the Save button in the Extracted insts... form displays the Save Instance Report form. For information on saving reports in parasitic aware design see Saving Report Data.

Probing Out-Of-Context and In-Context

In-context and out-of-context probing has particular relevance when you are performing backannotation and reporting on parasitics. A parasitic aware design permits out-of-context probing of post-layout simulation results, containing additional parasitic components. This type of probing is done on a schematic where the simulation used an extracted view.

With an out-of-context probe, parasitic aware design is referring to the view that is currently being displayed against the view that is specified in the configuration used for simulation.

You can run out of-context or in-context probing on simulation results only when the current designs have been simulated. See Simulating the Design in ADE Explorer.

Out-Of-Context Probing

Out-of-context probing occurs when you descend into any cellview other than the simulation cellview. For extracted views, parasitic aware design provides the functionality to map information from the schematic view to the post-layout view. You can reuse expressions created with schematic net and terminal names when simulating the extracted view and those net and terminal names are automatically mapped to their equivalent post-layout names.

Performing Out-Of-Context Probing in Extracted Views

To perform out-of-context probing in ADE Explorer or ADE Assembler, do one of the following:

1. Select the Results tab.
2. Right-click on an output value and select Plot.
   Or
3. In the Results tab, specify the plotting mode.
4. Choose the Extracted View or the Smart View next to Plotting Template.
5. Click the Plot All icon.
   The simulation results are plotted in the Virtuoso Visualization and Analysis XL window.

Alternatively, you can cross-probe using the Direct Plot functionality to plot the extracted net segments connected to instance terminals on different parts of the same net.

To use Direct Plot, do the following:

1. In the Results tab, right-click the extracted view output, and choose Direct Plot – Main Form. The Direct Plot Form appears.
2. Specify the Plotting Mode and click OK.
3. In the schematic view, right-click and choose Descend Read. Alternatively, use the bindkey E to descend into the extracted view on the schematic. The Descend form appears.
4. Specify the schematic view to descend into and click OK.
5. Choose a net or terminal in the schematic view.

Selecting a point on a schematic net probes the voltage on the nearest instance terminal. The selected points are plotted as waveforms in the Virtuoso Visualization and Analysis XL window and the schematic view is displayed.

In-Context Probing

In the parasitic aware design environment, in-context probing implies probing the same cellview that is specified in the simulation configuration.

• • A root cellview is always in-context.

Performing In-Context Probing in Extracted Views

To perform in-context probing, do the following:

1. In the ADE Assembler Results tab, right-click the simulation results for the Smart View and choose Direct Plot – Main Form. The Direct Plot Form appears.
2. In the schematic view, right-click and choose Return. Alternatively, use the bindkey Ctrl+E to return to the top-level testbench.
3. Select the instance that contains the Smart View. Ensure that the Smart View is selected to descend into and the mode is set to read-only. The Smart View is displayed.
4. In the Smart View, set the workspace to Basic.
5. Choose Window – Assistants – Navigator.
6. Choose a net in the Navigator Assistant. This plots the voltage on the net that you choose.
7. Do the following:
   • If you are using the extracted view:
     • Press escape to exit the Direct Plot mode.
   • If you are using the Smart View:
     • Choose Smart-Parasitics – Display Parasitics. The Display Parasitics form is displayed.
       The Smart-Parasitics Menu is displayed only in Virtuoso Layout Suite XL/GXL when you are working with a Smart View.
     • Specify the display settings and the threshold values for resistance and capacitance and click Apply. The parasitic display is updated with highlighted resistances and capacitances on the selected net.
     • In the Smart View window, click the Zoom In toolbar button to view the values of the parasitic resistances and capacitances.
     • Right-click a net in the Navigator and select Probe – Add. All nodes on the specified net are highlighted.
     • In the Smart View window, click the Zoom In toolbar button and select a square dot shape in the parasitic display. A small dot square represents a node on the net.
       
       Nodes can only appear in the parasitic display if the layer and location information for the specific node is available. The layer and location attributes are essential to create a physical handle to the node to allow viewing and selecting the node. This information is available in the display_map_file file. Ensure that this file is used if you want to display parasitics in the Smart View.
     • Choose Smart-Parasitics – Probe Node. A concatenated string consisting of the node ID and the net name of the node is displayed on the selected node. The same node information is also displayed in the Virtuoso Visualization and Analysis XL window with the segments plotted, as illustrated in the following figure.
       
       

An Analog Simulation Flow using PVS

This section discusses how parasitic aware design interacts with the Cadence Physical Verification and Extraction tools, PVS (Physical Verification System) and Quantus QRC (Resistance / Capacitance and Inductance Extraction), to create an extracted view.

Parasitic aware design functionality, such as parasitic probing and backannotation, can then be used to take account of the effect of parasitics. This can consequently improve the accuracy of your circuit simulation.

Parasitic aware design provides you with the functionality to annotate parasitic values including resistance (R), capacitance (C) and inductance (L) values on the schematic.

The following sections (not all of which are compulsory) will take you through a typical parasitic aware design flow in PVS:

• Preparing Cell Libraries
  • Preparing Library for Extraction
  • Planning Your Design Guidelines
• Creating an Analog Extracted View
  • Step 1: Comparing the Schematic and Layout Views Using PVS
  • Step 2: Building an Extracted View using Cadence Quantus QRC Extraction
  • Step 3: Building a Refined (Analog) Extracted View Using Parasitic Aware Design
• Backannotating Parasitic Values
  • Preparing for Resistance Backannotation (Running a DC Analysis)
  • Backannotation Labelling
• Performing Backannotation
  • Backannotating From the Parasitics Menu
  • Backannotating From ADE Explorer
• Reporting and Probing Parasitic Values
  • Reporting Parasitic Instances
  • Probing Parasitic Instances
  • Probing Buses for Parasitics
• Creating a Configuration
• Simulating the Design in ADE Explorer

Preparing Cell Libraries

Before proceeding to create an extracted view using Quantus QRC, you need to provide the following views and component description format (CDF) information for analog primitives and parasitic cells.

If required, the analogLib library contains examples of analog primitives and parasitic cells that you can copy to create your cell library.

You can find the analogLib in the following hierarchy:

$CDS_INST_DIR/tools/dfII/etc/cdslib/artist/analogLib

Preparing Library for Extraction

The following actions are required when preparing a library for parasitic extraction:

• Describe the technology layers.
  
  For details about technology layers refer to the Incremental Technology Databases and Display Resources User Guide.
• Add or modify the verification rules used by the PVS processes.
  PVS processes include:
  – Designed device extraction
  – Layout versus schematic (LVS)
  – Parasitic resistor and capacitor extraction (Quantus QRC)
  Refer to the Quantus QRC Extraction Users Manual for information on creating verification and extraction rules.
  
  You can use capacitance generation (capgen) to create the parasitic coefficients and files required for parasitic aware design.
• Prepare the PVS technology directory.
  This directory must contain all the designed device extraction rules, verification rules, and those files required for parasitic extraction.
  Again, refer to the Quantus QRC Extraction Users Manual for details about preparing the PVS technology directory.

Planning Your Design Guidelines

If you intend to extract parasitic components from the layout view and run a simulation with parasitics, you should use the following guidelines to avoid problems as you plan your design:

• Devices, with the componentName parameter (in auLvs simInfo), should be set to either:
  • pcapacitor
  • presistor
  • pinductor
  • pdiode
  • pmind
    
    This information is not directly required to run simulations with parasitics, but is necessary for parasitic probing between schematic and extracted views.
  If you do use these names to define your parasitics, be sure to set the appropriate values to ensure that they are properly reported.
• Do not use the LVS permuteDevice parameter to match groups of components in a series as that makes it impossible to determine which device to use for waveform probing.
• You can use the Quantus QRC ?LvsMatchRequired parameter to ensure that the extracted view can only be created if the layout and schematic match up.
• Set the permuteRule parameter for devices that have permutable terminals. Parasitic Aware Design uses this rule to detect terminals that have been permuted in the extracted view.

The syntax to set the permuteRule is "(p term1 term2)". For example, for a MOS device with a permutable drain and source, you can set the permuteRule parameter as "(p D S)". Similarly, for a resistor, you can set this parameter as "(p PLUS MINUS)".

Creating an Analog Extracted View

Before attempting to generate an extracted view you should ensure that the following requirements are met:

• You have successfully prepared your cell library (see Preparing Cell Libraries).
• The design adheres to the suggested design guidelines (Planning Your Design Guidelines).

With these tasks successfully completed, you will now utilize PVS to compare the layout view to the schematic view.

PVS creates an internally formatted database from the layout view (this database contains only the designed devices). Quantus QRC then reads the database to extract the parasitics and to create the extracted view. This extracted view contains designed devices and parasitic devices.

The steps required for the successful creation of a refined analog extracted view are as follows:

• Step 1: Comparing the Schematic and Layout Views Using PVS
• Step 2: Building an Extracted View using Cadence Quantus QRC Extraction
• Step 3: Building a Refined (Analog) Extracted View Using Parasitic Aware Design

Step 1: Comparing the Schematic and Layout Views Using PVS

1. Start the Cadence software by entering an appropriate command at the prompt, for example:
   virtuoso &
2. Choose File – Open in the CIW and open up a cell layout view to invoke the Virtuoso^® Layout Suite Editing window (for example, Layout XL).
3. In the Layout Suite Editing window, choose Launch – Plugins – PVS.
   The PVS menu is added to the menu bar of this window.
   
   PVS will need to be installed to be available as a plugin in the Layout window.
4. Choose PVS – Run LVS.
   The PVS LVS Run Submission form appears.
   
   
   
   You can use avCompareRule formGate(none) to ensure that the connectivity between the layout and schematic views are fixed. For more information on this, refer to the Physical Verification System User Guide.
5. If you want to load previously saved LVS run settings into the form, choose File – Load Presets and select a preset file name from the Load Presets File form.
6. To create a new LVS run, perform the following steps:
   1. Click Run Data to open the Run Data tab.
   2. On the Run Data tab, specify the path to the run directory in the Run Directory field.
   3. Click Rules to open the Rules tab.
   4. Specify the path of the technology mapping file in the Technology Mapping File field.
   5. From the Technology drop-down list, select a technology definition file for the process to be used.
   6. From the Rule Set drop-down list, select the name of the rule set to be used.
   7. Click Input to open the Input tab.
   8. Specify the library name, cell name, and view name of the layout and schematic views in the Layout and Schematic sections, as shown below.
      
      
      

1. 1. Click Output to open the Output tab.
   2. Ensure that the Create QRC Input Data option in the Additional Output section is selected.
      This option generates the data required by Quantus QRC to perform parasitic extraction.
   3. Specify a name of directory in the QRCDataDir field.
      A subdirectory is created by this name and the data required by Quantus QRC is saved in it.
   4. Click LVS Options to open the LVS Options tab and select appropriate options.
2. Click Submit to start a new LVS run.

The PVS Reports form is displayed. This form provides run status information. After the run is complete, the PVS LVS Run Status message box is displayed indicating the success status of the extraction results and the comparison results.

You can click Errors List on the PVS Reports form to display errors as the run progresses. For more details, see Checking LVS Run Report in the Cadence Physical Verification User Guide.

If there are errors, the tool prompts you to open LVS DE.

1. Click Yes to open the LVS Debug Environment and view the results and files of the LVS run.

For more details on how to debug an LVS run, refer to Debugging LVS Comparison Runs in Cadence Physical Verification User Guide.

Step 2: Building an Extracted View using Cadence Quantus QRC Extraction

Once the comparison between the schematic and layout views has completed, you now need to run Quantus QRC (Resistance/Capacitance and Inductance Extraction) to extract the parasitic devices and build the av_extracted view.

1. Select Quantus QRC – Run PVS-QRC from a layout session window.

The QRC (PVS) Interface form appears.

1. In the Design Cell Name field, specify a name for the design cell.
2. In the PVS/QRC Data Directory field, specify the path to the directory where the results of PVS were saved for Quantus QRC.

This is the same subdirectory name that you specified in the Output tab of the LVS Run Submission form. Refer to step k in the previous section.

1. Ensure that the required QRC technology library is selected in the QRC Tech Lib field and the technology name is selected in the Technology field.
2. Click OK to select the run.

The QRC (PVS) Parasitic Extraction Run form is displayed, as shown below.

1. On the Setup tab, ensure that either Extracted View or Smart View is selected from the Output drop-down box.
2. In the View field of the Setup tab, type the name of the view.

The default name for Extracted View is av_extracted, and in case of Smart View it is smart_view, but you can create the extracted view using another name.

On the Extraction tab, select an extraction type by using the Extraction Type drop-down list and specify options related to that extraction type.

1. Enter an appropriate entry (for example gnd!) in the Ref Node field of the Extraction tab.
   Ref Node is a capacitance extraction option for grounding caps. Capacitance is decoupled to the specified Ref Node.
2. Click OK to start the Quantus QRC run.

A progress form, which shows the progress of the Quantus QRC run, is displayed. When the Quantus QRC run is complete, a message box is also displayed showing the success status.

With the extracted view created, you can now use parasitic aware design to build an analog extracted view which can be used to filter parasitic devices.

For more information on Quantus QRC, see the Quantus QRC Extraction Users Manual.

Step 3: Building a Refined (Analog) Extracted View Using Parasitic Aware Design

The final step in this process is to build an analog extracted view using parasitic aware design functionality that is derived from the extracted view created using Quantus QRC.

1. Select Launch – Parasitics (in Schematics L/XL) from an extracted or schematic view.
   This will add a Parasitics menu to the schematic editor menu bar.
   
   The Parasitics menu is displayed by default when you are working with ADE Explorer or ADE Assembler.
2. Select Parasitics – Setup from the Parasitics menu.
   This will display the Setup Parasitics form where you can specify which views to use. If opened from a schematic you will only need to specify which extracted view to use (and vice versa).
   
   
3. In the Extracted Cellview section, ensure that you have selected the av_extracted view that was created in Step 2: Building an Extracted View using Cadence Quantus QRC Extraction.
4. Click the OK button to setup parasitics.
5. Select Parasitics – Refine Extracted View from the Parasitics menu.
   This will display the Refine Extracted View form.
   
   
6. Enter the new extracted view name in the View Name text field. The default refined analog extracted view name is av_analog_extracted.
   
   If this field is not completed, and you attempt to run Refine Extracted View, the following message will be displayed in the CIW log window:
   WARNING: No analog view name specified. Specify a name in the ’Refine Extracted View’ form under the Analog Extracted View Name field.
7. Click OK.
   The Refine Extracted View form closes and av_analog_extracted (or your renamed view) is created and available for parasitic aware design.
   After the refine extracted view has been created, a window is displayed summarizing the parasitics in the new view. This information is also outputted to the CIW.

Backannotating Parasitic Values

Preparing for Resistance Backannotation (Running a DC Analysis)

Backannotation of resistance values is dependent upon the results of a DC analysis of the extracted view. Whole net probing and the design report (see Parasitics – Report Parasitics) also make use of the DC analysis results. In all cases, the requirements on the simulation data are the same.

This section therefore describes the actions and requirements you must perform and meet to provide suitable simulation data.

• Action 1: Provide and configure a suitable testbench that uses Spectre to simulate the chosen extracted view

Requirements:

• The testbench must ensure that all nets in the design are stimulated.
• It does not matter where in the hierarchy the extracted view appears, as parasitic aware design uses the hierarchical instance path to locate the simulation results for the extracted view that corresponds to the out-of-context schematic.
• When backannotation is invoked, the configuration (see Creating a Configuration) bindings must match those that were in place during simulation. This is required, as problems could arise if you change and save the config after a simulation is run.
• Action 2: Run a simulation of the testbench that includes a suitably configured DC analysis

Requirements:

• The analysis must be configured to save DC operating Point. This is part of the DC Analysis in Spectre and the Transient Analysis in Ultrasim.
  
  For information on running a DC operating point analysis, see Setting Up for an Analysis in the Virtuoso ADE Explorer User Guide.
• The analysis must not be swept.
• The DC analysis must use the gmin simulator option to ensure that the current flows through nonlinear devices and nets with no DC path to ground.
  The gmin value should be set low enough so as not to impact the DC solution. Setting the gmin value as low as possible will also provide for more accurate effective R results. Spectre or Ultrasim - the simulators that support Effective R Calculations - will issue a warning if the gmin value is too high. However, the lower the gmin value, the increase in the likelihood that the simulation will not converge. Additionally, you may also want to consider attempting to create a R-only extracted view which could reduce the influence of capacitors on the net.
  Using the gmin convergence option is the default.
  
  If the gmin influence is significant, in terms of the net current, then the resistors placed around the capacitors, for a dcOp calculation, will create a significant contribution to results, and will be reflected as distorted resistance values. For example, if you receive the gmin warning, R values may be reported in the 100 megohm range, when in fact they are in the ~10 ohm range.
  If you are caught between the choice of continuing with no convergence or proceeding with a value that generates a gmin warning, you should proceed with the warning-generating value, but only consider returned backannotation values as “approximations”, suitable only for quick feedback.
  You can set the gmin option in the Simulator Options form, which is accessible via an ADE Explorer window by selecting Simulation – Options – Analog in the Resistance Options section (in ADE Explorer or ADE Assembler if you right-click on a Spectre or UltraSim test, an Options – Analog selection will be displayed). For more information on adjusting Spectre’s tolerances, see the Spectre Circuit Simulator User Guide - Identifying Problems and Troubleshooting chapter.

Running the testbench simulation will produce two datasets of interest:

1. dcOp
   A dataset that contains all saved node voltages.
2. dcOpInfo
   A dataset which contains DC operating-point data for each instance in the design. This will include terminal currents, voltage drop between terminals, and device power consumption.

Effective R Calculations

An effective R value is a single number distillation of complex physical parasitic networks, including power dissipation and current. The use of a single number makes annotation to each logical net of the schematic possible. You can use this single effective R value, per net, to monitor changes to the layout that are made at each iteration request. This will check and confirm that you are correctly reducing the parasitics on key nets.

This value also normalizes the parasitic network on each net, even though the parasitic network itself may be considerably different between iterations. This could be due to changes in the layout of the net, or the layout around it, that influences its parasitics, for example the number of parasitic elements and connectivity. Alternatively, parasitic networks could also change as a result of Assura parameters, such as fracture length.

The DC simulation results are used to calculate the backannotated resistance. These results can have different values for the same design, based on the value of gmin compared to the design component values (see also Preparing for Resistance Backannotation (Running a DC Analysis).

Calculation of effective R is based on the current at the source (iS) and drain (iD). If iS == 0 and iD == 0 then effective R is not calculated as there is no current flow and no power. If either of iS or iD is a non-zero value, effective R is calculated as:

Where,

I is current at source if , or

I is current at drain if

There may be a few thresholds involved while working out the current. For example, there can be an initial threshold from the DC-OP attribute “abstol(I)”. If this does not exist, then the environment variable, mspsAv currentThreshold, is used. If the environment variable is missing, is used.

Effective R value is a measure of the power lost through the parasitic resistor network (or equivalently, the delta between the power entering the network and the power leaving the network), normalized by the total current entering (or leaving) the network.

Combining V=IR with P=VI, it is calculated as:

where:

P is the sum of the power through the parasitic resistors in the network.

I is the current entering (or leaving) the network.

There could be situations where the capacitor was annotated correctly, but the effective resistance is not annotated on each node. In such cases, the Spectre log reports that a large number of parasitic resistors, pRes, have been reduced when the Enable Post Layout Optimization option in the High Performance Simulation Options form is used. This is why currents for parasitic resistors, pRes, are not saved by Spectre and parasitic aware design reports effective R as 0 for most of the nets.

To see the effective R when effective R annotations are not available, deselect the Enable Post Layout Optimization option in the High Performance Simulation options form.

Backannotation Labelling

Assuming that you have suitable simulation results at hand (see Preparing for Resistance Backannotation (Running a DC Analysis)), backannotation can be performed.

Parasitic aware design provides you with the functionality to annotate parasitic resistance (R), capacitance (C) and inductance (L) values on the schematic when Parasitics – Show/Hide Parasitics is used.

• Analog Designers use many tools and techniques, including dynamic-analysis tools such as simulators, and static-analysis like parasitic aware design, to understand the impact that the post-layout parasitics have had on their previously “ideal” design. In order to identify spots where values of parasitic resistance are a concern, designers want to display and analyze the resistance values of these networks of resistors using parasitic aware design and ADE Explorer or ADE Assembler/Schematics L/XL. Physical hot spots are identified as unacceptably large values annotated onto logical schematic nets by parasitic aware design. For resistances, these values represent the ‘effective resistance’ of each net (see Effective R Calculations), regardless of the complexity of the parasitic networks that each represents, or the number of net terminals.
  • ~ label
    If a net has two or more terminals, the R value will use an approximation symbol (~) to indicate that the value uses the delta power method to approximate a resistance for the net.
  • - - label
    The “- -” label indicates that you have backannotated without any simulation results being set up.
  • NA label
    If the necessary simulation results are not available to allow delta power calculations for specific nets, for example, where a subset of voltages or currents have not been saved, the annotated R value will display the string “NA” for “Not Available”.
    If a string with NA is displayed, a (one off) message will be displayed in the CIW as follows:
    “Parasitic R values are not available due to missing/incomplete simulation results. Please run a DC analysis and supply the path to the results directory via the Parasitics Setup form.”
  • NS label
    If a net is not stimulated during simulation, the current through it will be 0, which makes it impossible to calculate an effective R value. in such cases, the annotated R value will be the string “NS” for “Not Stimulated”.
    If a string with NS is displayed, a (one off) message will be displayed in the CIW as follows:
    “Effective R values are not available on nets with no stimulus (nets with ‘r=NS’). Review the simulation test bench to ensure that there is current through the net and resimulate.”
    
    “Not stimulated” basically means having no current flowing through the net. This can occur in DC simulation if all the parasitic resistances are removed from the net. For example, if the extraction did not include R extraction, or if the extracted view, that is being simulated, has been refined so that parasitic Rs have been removed from the net.
• The value displayed for C is an arithmetic sum of parasitic capacitance.
  • Σ label
    The C value will use a sigma (Σ) sign to indicate that it is a sum of the parasitic capacitances associated with the net.
• The value displayed for L is an arithmetic sum of parasitic inductance.
  • Σ label
    The L value will also use a sigma (Σ) sign to indicate that it is a sum of the parasitic inductance associated with the net.

Persistence of Backannotation Labels

If you open a schematic cellview in edit mode, and perform backannotation, the backannotated labels will be persistent, and be written to the schematic database. However, if you open the schematic in read-only mode, the backannotated labels will only be temporary.

Performing Backannotation

Backannotation functionality is available through:

• The Parasitic menu in Schematics L/XL
• The Results – Annotate menu option in ADE Explorer

Backannotating From the Parasitics Menu

For backannotation purposes, you can access parasitic aware design functionality, from a schematic window, by selecting Launch – Parasitics (in Schematics L/XL) to display a Parasitics menu (for more information see Parasitics Menu). There is a Show/Hide Parasitics toggle menu-item to inform you if annotation is currently active or not.

If you are attempting to backannotate via the Parasitics menu, you should first of all consider the following scenarios:

Scenario 1: The Current Schematic Window is Associated With a Current ADE Session

Here, the Show/Hide Parasitics toggle menu-item is identical to that in ADE Explorer (see Backannotating From ADE Explorer) and operates in the same manner. That is, no parasitic aware design setup is required to enable the Show Parasitics menu because the required information is available from the ADE session.

Scenario 2: The Schematic Window is NOT Associated With a Current ADE Session

In this scenario, you are required to perform the parasitics setup step (see Parasitics – Set Up) so that parasitic aware design can locate the simulation results directory and extracted views.

Only after setup is completed will you be able to annotate parasitic values.

Verifying a Configuration Setup

When a configuration setup (Parasitics – Set Up) is used, you can specify the design that was simulated, the simulator, and the simulation results directory. When you click the OK or the Apply buttons in the Setup form, parasitic aware design will check that the results directory is valid and will also verify that it contains the dcOp and dcOpInfo datasets. If the directory specified does not meet these requirements, an error will be displayed and the Show Parasitics menu-item will remain disabled.

Where a schematic is associated with an ADE session (Scenario 1 above), the Setup parasitics form will still be available. The simulation cellview, Simulator, and Results Directory for R Calculation fields will mirror the settings in the Analog L session and will consequently be disabled. This therefore means that you cannot change any parasitic aware design settings so that they are out of sync with ADE. It also indicates that other parasitic aware design functionality must use the simulated design from ADE, when available, to determine what extracted view to use, and that other parasitic aware design functionality must be able to operate under a configuration.

Backannotating From ADE Explorer

Setting up parasitics (see Parasitics – Set Up) is normally required before parasitic aware design functions are enabled. However, with all the information, that parasitic aware design requires to determine the extracted view being available in the ADE session, along with the simulation results directory, the setup step is not required.

Backannotating from ADE Explorer therefore requires the following steps:

1. ADE Explorer must be started from the top-level schematic of a configuration view. You must therefore open a configuration view, then open the top-level schematic view.
   
   If ADE Explorer is already open, you can choose the configuration by selecting Setup – Design and choosing the appropriate design.
2. Select Launch – ADE Explorer to display the Virtuoso ADE Explorer window.
   
   
3. From here, select Results – Annotate.
   This displays a sub-menu which includes Show Parasitics and Hide Parasitics. The Show/Hide Parasitics menu entries are enabled dependent upon whether parasitic aware design is active or not.
   
   Results – Annotate is only enabled when dcOp point simulation results are available. That is, parasitics will only be shown when effective resistances (see Effective R Calculations) can be calculated using the results. It will not be enabled to show basic results with R=N/A with any other type of simulation results.
4. Click the Show Parasitics menu option.
   Selecting Show Parasitics causes the schematic editor window, associated with the current ADE Explorer session, to show parasitic annotations when displaying in an out-of-context schematic. When the schematic is in-context, no parasitics will be displayed and a message is displayed in the CIW to inform you why there are no annotations. As you navigate through the schematic hierarchy, the annotations will change as appropriate.
   If the DC simulation results do not include the necessary data for a specific net, then an annotation of “NA” (Not Available) will be set.
   Parasitic annotation will remain active until you choose to Hide Parasitics.
   
   If there are no DC simulation results available (see Backannotation Labelling), and C annotation is disabled, Show Parasitics will be grayed out. Likewise, if there has been no extracted view specified in the config.

Reading Simulation Results

You can change where the directory simulation results are read from by using the Results – Select option in ADE Explorer.

ADE Explorer uses this directory when plotting data, annotating schematics, and annotating parasitics. Parasitic aware design looks for the dcOp and dcOpInfo datasets in the current simulation results directory. If you run a new simulation in ADE Explorer, ADE Explorer will send a message to parasitic aware design to hide backannotation labels, if they are visible, and discard any backannotation that is cached.

Reporting and Probing Parasitic Values

By probing the schematic av_extracted or Smart View, you can examine the instances of parasitic components. The name, value, and net connectivity can be displayed for each parasitic instance.

To view the parasitic instances in the av_extracted view for probing, the interconnect layers need to be marked as selectable in the layer selection window (LSW). Use the AS (All Selectable) button in the LSW to make all the layers selectable (AS is the default).

In the extracted view, the terminals are not readily accessible. For example, they could be minuscule terminals on the pcapacitors, or they may not exist at all, as in the case of devices which are now just rectilinear layers.

Therefore, in the extracted view, you are required to select the net segments. The net names, such as “1:netX”, “2:netX”, and so on, come from PVS, and parasitic aware design does not have any control over the name ordering or continuous nature of the numbers. For example, for the schematic net “NetX”, the extracted view segment could be “1:netX”.

In summary, net-to-net probing, in the extracted view, returns parasitics between the selected net segments, rather than maintaining the same definition, as in the schematic view, where parasitics between the two “whole” schematic nets are returned.

Reporting Parasitic Instances

To probe parasitic values, you should perform the following:

1. Select Parasitics – Report Parasitics.
   If the Parasitics menu is not on view in the current session window, you can display it by selecting Launch – Parasitics (in Schematics L/XL).
2. Choose, from the sub-menu items, what kind of probing you want to perform: Net, Net to Net, Terminal to Terminal, Net Capacitors or All Nets.
   For more information on these options see Parasitics – Report Parasitics.
   Selecting any of the first three report options listed (Net, Net to Net, Terminal to Terminal) will display the Parasitics report form. Go to Step 3.
   Selecting Net Capacitors will display the Capacitors for net form. Go to step 4.
   Selecting All Nets will display the All Parasitics (Design Report) form. Go to step 5.
   
   The NA label indicates that Parasitic R values are not available due to missing or incomplete simulation results.
3. The Parasitics report form allows you to choose which parasitic values and information to Display: R, decoupled C, coupled C, self C, L, and/or K (for descriptions of these values see Display options).
   You can sort the table by clicking on the required column header and save the report contents to a separate .txt or .csv file.
   See also Probing Parasitic Instances.
4. The Capacitors for net report form displays the summed capacitances (Sum C) between the net and all nets that it is connected to via parasitic capacitors. No report will be generated for “0” capacitances, and no distinction is made between power/ground, and other nets.
5. The All Parasitics form (Design Report) lists each net in the design, and the total value for the net, based on either the estimated or summed value. Again, the report information can be saved in either .txt or .csv format.
   For more information on the All Parasitics form, see Reporting on All Nets.

If you select a parasitic instance from the Parasitics report form, and the extracted view is open, then the extracted view is zoomed to the component symbol associated with the parasitic instance, and the cursor is moved to rest on the symbol (the From and To nets are also highlighted).

This zoom feature works for the Net, Net to Net, Terminal to Terminal and Net Capacitors options.

Probing Parasitic Instances

• For Terminal to Terminal options click two pins or instance pins in the schematic or nets in the extracted view to collect all the parasitics between two points.
• For Net to Net options click two nets in the schematic or extracted view to collect parasitic capacitances between two different nets.
  To perform Net to Net probing, you must run Quantus QRC extraction using coupled capacitors (choose Coupled in the Cap Coupling Mode drop down list on the Extraction tab of the Quantus QRC Parasitic Extraction Run form).
  A list of the collected parasitic instances appears. Select an instance from this list to highlight the component symbol associated with this parasitic on the extracted view.

Probing Buses for Parasitics

To probe parasitic values in a bussed net, you should perform the following:

1. Select Parasitics – Report Parasitics.
2. Choose either Net (continue to step 3), Terminal to Terminal (step 4), Net to Net (step 5) to display the Parasitics for net form.
3. For information about parasitics on whole nets, click a bus in the schematic view to display the bits in the Select bits from bus form. Then:
   1. Choose the bits of interest from the list (to select multiple bits, click and hold the Shift key while you select the bits, or choose the Select All option) and then click the OK button.
   2. The parasitics report form appears and none is displayed in the Select cyclic field (default state).
   3. Choose one or all of the bits in the Select cyclic field (use Select All to select all bits).
      An ordered list of the parasitics for the selected bus bit or bits appears.
   4. Sort the parasitics by R, decoupled C, coupled C, L, and/or K as required.
   5. Click Save to write the probed parasitics to a file.
      The Save Parasitic Probes form appears.
   6. Enter the filename into the Filename field and click OK.
4. To collect all the parasitics between two points (terminals), click Terminal to Terminal, then select bits from the first bus terminal. The bits in the second terminal are automatically matched to the bits in the first terminal. Both selected terminals must be connected to the same net in the schematic. Then:
   1. Choose the bits of interest from the Select bits from bus form.
   2. Choose one or All of the terminal pair bits from the Select cyclic field in the parasitic report form.
      
      The Select Leaf Terminals form may appear if the selected terminal(s) have more than one leaf terminal. You will be asked here to firstly select the terminals you want to measure resistance values for.
   3. Click Save to write the probed parasitics to a file.
5. To collect all the parasitics between two nets, click Net to Net and then select bits from each of the bus nets in the schematic view. Then:
   1. Choose the bits of interest from the Select bits from bus form.
   2. Choose one or all of the bits from the two Select cyclic fields in the parasitic report form.
      The Select cyclic fields contain the selected bits for the two nets.
   3. Click Save to write the probed parasitics to a file.
6. To probe a bus for net capacitors, click Net Capacitors and then click a bus in the schematic view to display the bits in the Select bits from bus form.
   1. Choose the bits of interest from the list (to select multiple bits, click and hold the Shift key while you select the bits).
   2. Click OK.
      The parasitics report form appears and none is displayed in the Select cyclic field (default state).
   3. Choose one or all of the bits in the Select cyclic field (use All to select all bits).
      An ordered list of the parasitics for the selected bus bit or bits appears.
   4. Click Save to write the probed parasitics to a file.
      The Save Parasitic Probes form appears.
   5. Type the filename into the Filename field and click OK.

Creating a Configuration

This section explains how to set up a configuration so that the simulator will run with the av_analog_extracted view.

The steps listed here for using the Hierarchy Editor to create a configuration are abbreviated. For complete information, see the Cadence Hierarchy Editor User Guide.

To create a configuration for your design:

1. From the CIW, choose File – New – Cellview.
   The Create New File form appears.
2. Choose the Library Name for the new file.
3. Enter the Cell Name that you want to create the configuration for.

The top-level cell of your design is usually appropriate for use.

1. Enter the config name you want to use into the View Name field.
2. Choose Hierarchy-Editor from the Tool drop-down list box.
3. Ensure that the Library path file field correctly specifies the cds.lib file that contains the paths to your libraries.
4. Click the OK button.

The Hierarchy Editor along with the New Configuration form is displayed.

1. In the New Configuration form, click the Use Template button located at the bottom of the form.

The Use Template form appears.

1. Select a template that is compatible with the simulator you are running from the Name drop-down list, for example spectre.
2. Click OK in the Use Template form.
   The New Configuration form redisplays with default data for the Top Cell and Global Bindings sections. This allows you to modify a typical View List and Stop List, rather than creating them from scratch. Templates exist for each of the simulators.
   To create templates that provide defaults for these fields, see the Cadence Hierarchy Editor User Guide.)
3. In the Top Cell section, enter the Library, Cell name, and schematic cell View from which to build the configuration.
4. Click OK.
   The Hierarchy Editor window displays your data.
   The Hierarchy Editor window configures the design by using a default View List and Stop List in the Global Bindings section. You need to modify these lists for your design.
5. Use one of the following methods to specify the extracted view for the cells or blocks for which you want parasitics simulated.
   

   To specify views for individual blocks

   To specify views for multiple blocks

   In the Instance Binding section of the Hierarchy Editor window, position the cursor in the View To Use column of the appropriate block. If the Instance Binding section is not visible in the window, select View – Instance Table to display this section. Press the right mouse key to display a list of commands. Choose Select View to display the list of views for this block. Choose extracted as the view for this block.

   In the Global Bindings section of the Hierarchy Editor window, add extracted as the first view in the View List text field. This ensures that the extracted view is the selected view for every cell that has an extracted view.

   The extracted view mentioned above could be either av_analog_extracted or av_extracted.
6. Choose View – Update to reconfigure the design to reflect your changes.

The Update Sync-up form appears.

1. Click OK.
2. Choose File – Save to save the configuration with your changes.
3. Choose File – Exit to close the Hierarchy Editor.
   
   After you have created your configuration, you must descend out-of-context (descending into any cellview other than the simulation cellview) before simulating the design.

Simulating the Design in ADE Explorer

Before you can run a simulator with an extracted view, you must first of all set up a configuration (see Creating a Configuration).

After a successful simulation, you can select terminals and device pins on the schematic, and use the plot commands to display and probe the results in a waveform window. The resultant waveforms can then be used with ADE calculation and analysis tools.

To run the simulation:

1. In the config top-level schematic window, select Launch – ADE Explorer.
   The Virtuoso Analog Design Environment simulation window appears.
2. Choose Setup – Design.
   The Choosing Design form appears.
3. Choose the Library Name and Cell Name of your design.
4. Select the config View Name for your design.
5. Click the OK button.
   This view supplies configuration as well as schematic information.
6. Back in the Analog L simulation window, choose your simulator, model path, environment variables, analyses, and simulator options.
7. Choose Simulation – Run.
   When the simulation run completes you can select outputs and probe the design on the schematic.
8. Choose Outputs – To Be Plotted – Select On Schematic.
   
   You can also use the Results – Direct Plot... options.
9. To select current outputs, click terminals in the schematic or in the extracted views of the blocks where parasitics were extracted.
   To select voltage outputs, click nets in the schematic or in the extracted views of the blocks where parasitics were extracted.
   
   The only places where connections on different views are guaranteed to match are on component terminals.
   The names of the selected signals are listed in the Outputs section on the Virtuoso Analog Design Environment simulation window.
   
   Irrespective of the view from which the signals are selected, their names listed in the Outputs section are always taken from the schematic view.
10. Choose Outputs – Plot Outputs. Outputs will be plotted in the Virtuoso Visualization and Analysis XL window.

If the output contains calculator functions with net names, in case of out-of-context probing, the net names might change for different extracted views. In such case, you can use the axlMapInstTermToNet SKILL function to dynamically obtain the net connected to a particular instance terminal in the extracted view from inside calculator expressions.

For information on running a simulation in ADE Explorer or ADE Assembler see the Running a Simulation chapter in the Virtuoso ADE Explorer User Guide or the Virtuoso ADE Assembler User Guide.

Out-of-context Probing in ADE Explorer

A cellview is said to be in context when it is the view that is "bound" via configuration, that is, the view that is picked up by the simulator.

A view can therefore be classified as being out of context when it is not the current bound view. For example, if you want to use an estimated view in your simulation, you need to set up a configuration that will override the default view for one or more instances, likely to be schematic, to be the estimated view.

When you now simulate this design, any views that are bound to the estimated view will be netlisted to include the parasitics in them.

Performing Out-of-Context Probing

To perform out-of-context probing in ADE Explorer, right-click on an output value and select either:

Results - Direct Plot - Transient Signal

or

Results - Plot Outputs - Transient Signal.

ADE Explorer plots the output in the Virtuoso Visualization and Analysis XL window and also opens the schematic view. Next, descend into a view that is not an estimated view, for example, the schematic view.

To probe a signal, click the voltage signal at a point close to the terminal. The probe automatically jumps to the closest terminal on that net. An X appears on the selected terminal. You can select several terminals on the same net. Each selected terminal is marked with a different color X. The associated waveform displays in the same color as the X on the schematic.

If the output contains calculator functions with net names, in case of out-of-context probing, the net names might change for different extracted views. In such case, you can use the axlMapInstTermToNet to dynamically obtain the net connected to a particular instance terminal in the extracted view from inside calculator expressions

For information on running a simulation in ADE Explorer, see the Running a Simulation chapter in the Virtuoso ADE Explorer User Guide.