Product Documentation
Virtuoso MultiTech Framework User Guide
Product Version IC23.1, November 2023

Moving Pins to Bumps

Typically, when a layout design is generated using either Floorplan – Generate Physical Hierarchy or Connectivity – Generate All From Source, all generated instances and pins are placed below the PR boundary, at the same relative positions as in the schematic.

In the Virtuoso Stacked Silicon solution, after defining connectivity for bumps and TSVs, the next step is to move pins to the corresponding bumps based on their connectivity information.

Virtuoso Stacked Silicon solution provides the following commands to move pins to bumps:


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