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Contents

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1

Introduction to Virtuoso Multi-Technology Solution

Virtuoso Multi-Technology Solution Setup

License Requirements for Virtuoso Multi-Technology Solution

2

Unified Libraries

Views in the Unified Library

Schematic Symbols

Component Footprint Views

Component Definitions

Variant Definitions in CSV Files

Component Modeling

Padstacks

Symbol Definitions

Components and Symbols

Types of Libraries for Creating Unified Libraries

Exported Die Library

BGA Library

Tline Library

pkgLib Library

Passive Component Library

CSV Import Library

Unified Library Validation

Converting Allegro Libraries to Unified Libraries

Netlisting Setup for Unified Library Components

3

Import Libraries and ICs

Create Technology File

Import Technology File

Update Technology File

Constructs in the Technology File

Library Import

Die/TILP Instantiation

Die Export Preparation

Exporting Dies

Edit Die Layout and Abstracts

Creating and Verifying Integrity 3D-IC Compatible Die Abstracts

Die Audit

Creating TILPs

Alternate Footprints in TILPs

TILP Versions

Replacing Pads

4

Package Schematic Creation

Instantiating SMD Instances

Instantiating BGA Instances

Instantiating IC Instances

Creating TLines Instances

Instantiating TLine Instances

Creating and Saving Connectivity Information in Package Schematic

5

Package Layout Creation

Generate from Source

Dies in Virtuoso Multi-Technology Solution

Wirebonded Dies

Flip Chip Dies

Guides in Wirebonded Dies

Creating a Guide

Editing a Guide

Bond Wires and Bond Fingers Creation

Creating Bond Wires and Bond Fingers

Creating Bond Finger Definitions

Moving Bond Wires and Bond Fingers

Updating the Finger Attach Point

Setting a Bond Wire Profile

Flip Chip Parameters

Types of Bump Attachments

Configuring a Module Stack

Thermal Shrink Factor

Creating a Curved Polygon

Creating a Curved Rectangle

Interactive Routing in Virtuoso RF Solution

Managing Curved Shapes in Wire Editor

Push-and-Shove Feature

Fillet Creation Between Curved Path and Other Objects

Void Shapes

Void Shape Generation

Create Dynamic Shapes

Create Signal Shapes

Generate Void Shapes

Convert Selected Dynamic Shapes

Smooth and Trim Void Shapes

Package Constraints Supported by the Void Generator

Dynamic Shape Priority

Extracting Connectivity Information from Package Layout

6

Interoperability with SiP

Export Package Layout

Complete the Package Layout

Manual and Automatic Placement

Placement Tasks

Routing Tasks

Importing the Package Layout

Rebinding the Layout to a Schematic

7

Verify the Package

Cross-Fabric Checks Run

Performing Cross-Fabric Checks

Checking Layout Against Schematic

Extracting the Connectivity

Performing DRD Checks

Supported DRD Constraints and Checks

8

Edit-in-Concert

Update Binding Information

Viewing Die Instance Annotations

Key Edit-in-Concert Views

Launch Edit-in-Concert Mode

Modify in Edit-in-Concert Mode

Movement of Dies in Edit-in-Concert Mode

Movement of Die Instances in Edit-in-Concert Mode

Placement Status of IOs

Changes to TILP Parameters in Edit-in-Concert mode

Change from Package view to Layout View

Net Tracing in Editing-In-Concert Mode

Probing a Design in Edit-in-Concert Mode

Checking and Fixing IO Pad Locations

Running the LVA Checker

Running the LVA Fixer

IO Pad Connectivity Mismatch Fixes

IO Pad Number Mismatch Fixes

Exiting Edit-in-Concert Mode

View-in-Concert Mode

9

Stacked Modules Management

Stacked Modules

Benefits of Implementing Stacked Modules

Components of a Stacked Module

Stacked Module Assemblies

Configuring a Stack

Die Operations

Creating Bumps and TSVs

Assigning Connectivity between Bumps

Unassigning Bump Connectivity

Deleting Unassigned Bumps

Moving Pins to Bumps

Updating Bumps to the Abstract View

Saving Bumps to File

Creating Bumps from File

Inter-Die Operations

Propagating Bumps

Fixing Bump Alignment Violations

10

SiP Layout Creation

Creating a SiP Layout from a Package Schematic

Generating a SiP Layout from a Source Schematic

Checking Against Source Schematic

Creating an Extracted View

11

Schematic Creation from SiP File

Creating a Schematic Layout from a SiP File

12

Assisted Import and Export

Updating a Virtuoso Layout From a SiP File

Virtuoso Layout to SiP with Assisted Export

Initial SiP File to Virtuoso RF Solution Database

Cell Replacement

13

SiP DRC Checker

Performing DRC Checks in Virtuoso RF Solution

A

Virtuoso Multi-Technology Forms

Allegro Design Layout Importer Form

Annotate From Extracted View Form

Cell Replacement Form

Cell Replacement Dashboard Form

Convert Allegro Libraries to Unified Libraries Form

Create Extracted View Form

Create MultiTech Schematic Form

Export Design Update Form

Pad Stack Replacement Form

SiP DRC Check Form

Virtuoso Multi Technology Enablement Form

XOR SiP against OA Form

Add Bond Finger Definition Form

Add Layer Form

Batch Checker Form

Bind Layout Form

Bump and Ball Editor Form

Bump Connectivity Assignment Form

Bump Propagate Form

Configure Module Stack Form

Create Bond Wire Form

Create Bump and TSV Form

Create Guides Form

Create TILP Form

Cross Fabric Check Violation Summary and Navigation Form

Die Instance Annotations Form

Edit Instance Properties Form (Die/Package TILP Parameters)

Export Bump Info Form

Export Die Form

General Settings

Advanced Settings

Pin Numbering

Area Transfer

Import Bump Info Form

Import Die Text File Form

Layer Stack Editor Form

Set Bond Wire Profile Form

Virtuoso RF Compliance Audit Form

Virtuoso Multi Technology Options Form

B

Virtuoso Multi-Technology Environment Variables

optionalPartData

vsdpSparamCSVModelNameField

vsdpSpiceCSVModelNameField

areaTransferFile

bondFingerAlignment

bondFingerProfile

bumpCenterMismatchCheck

casDieLayoutVsAbstract

cdfParamPromptLineNumber

checkerPrecisionFactor

createNoConn

createWireFingerOrBoth

csvFile

customizePin

deleteViewsBeforeExport

dieTemplateFile

distributeObjsOnGuide

drdEditApkDrcBlockageOverlapCheck

drdEditApkDrcComponentOverlap

drdEditApkDrcShortCheck

exportNoBumpTerm

honorConstraints

icSymbolCheck

ignoreColumnNumbers

ignoreLineNumbers

instTermLabelCheck

ioCheck

layoutConnectivityFile

layoutConnectivityPinNamesChkBox

libraryCheck

noConnCell

otherChecks

outputMode

paramMap

paramNameLineNumber

partNameToImport

pinNumberFile

pinOrdering

pinOrderingCustom

sameTechnologyAbstract

schematicConnectivityFile

schematicConnectivityMode

segSnapMode

shortPinCell

shortPinLib

snapEndPoint

snapMode

termsCheck

transferArea

voidGeneratorTrimUnconnectedShapes

C

Virtuoso Multi-Technology Solution SKILL Functions

vmtCompareSipToOa

vmtcsvCreateComponentCellViewsFromCsv

vmtcsvInstallCsvFile

vmtLibImport

vmtValidateUnifiedLibrary

vrfCheckTILPVersion

vrfComplianceAudit

vrfExportLayoutSkill

vrfExportPackage

vrfLowerPriority

vrfHiUpdate

vrfRaisePriority

vrfSipSet

vrfSipGet

vrfTLineAbut

vrfUpdateTILPVersion

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