Supported DRD Constraints and Checks

DRD supports the following constraints for verifying a layout.

• pkgMaxBondwireLength
• pkgMinBondwireLength
• pkgMinBondwireSpacing
• pkgMinBondwireWidth
• pkgMinHoleSpacing
• pkgMaxLineWidth
• pkgMinLineWidth
• pkgMinSpacing

The following DRD checks are performed for verifying a layout.

Overlap Checking

DRD checks if the PR boundaries of two SMD or die instances placed next to each other overlap. If the Pcell parameter of the instances, flipOverY, is set to nil, they are placed on the top of the board. If the parameter is set to t, the instances are placed on the bottom of the board. In either case, the PR boundaries of the instances must be non-overlapping.

To perform overlap checking, select the Component Overlap Check check box on the Process Rules page of the Batch Checker form. Alternatively, set the drdEditApkDrcComponentOverlap environment variable to t in your .cdsinit or .cdsenv file.

Supported Net Overrides

DRD supports the following net overrides for verifying a layout:

• Net: Set of constraints applied to a net
• Net Group: Set of constraints applied to a group of nets
• Net Class: Set of constraints applied to a mix of nets and net groups
• Net Class-Class: Set of constraints applied between two net classes

For more information on net overrides, see Allegro® Platform Constraints Reference and Allegro® Constraint Manager User Guide.

DRD Region Overrides

DRD supports region overrides for verifying a layout. A layout can have multiple regions, with each region having a separate set of region-specific constraints. All shapes in a region are checked against their own region-specific constraints.

Region-specific constraints override net, design, and foundry constraints. When regions are hierarchical, the constraints of an inner region override the constraints of outer regions.

For more information on net overrides, see Allegro® Platform Constraints Reference and Allegro® Constraint Manager User Guide.

Reporting minSpacing and Short Violations

DRD reports minSpacing and short violations between shapes on top-level nets and shapes on local nets, which are shapes in the hierarchy with no top-level net. However, DRD does not report such violations for a shape on the top-level net in the minSpacing halo around the same top-level pin.

For example, consider an inductor that has pins on nets A and B and its coil shape over net C. DRD reports short violations between the inductor coil shape and all nets at the top level, except when a shape on the top level of net B is within the minSpacing value for pin B. This allows the connection to pin B without DRC violations. DRD reports shorts violations for shapes on net A that are near pin B and for shapes on net B that are near pin A.