Setup File Template

lpSetupOptions = '(nil

 ;;; Supply Nets

 supplyNets (nil

  monitor (nil

   names ("VDD_PROBE" "VSS_PROBE")

   regExprs ("VDD_PROBE*" "VSS_PROBE*")

  excludePG (nil

   names ("OUTVDD")

   regExprs ("OUTVDD*")

  ground (nil

   names ("Vss" "Vssa" "Vss_Int")

   regExprs ("[vV][sS][sS]")

  power (nil

   names ("Vdd_1v8" "Vdd_3v3" "Vdd_Int")

   regExprs ("[vV][dD][dD]" "[vV][cC][cC]")

 ;;; Supply Net Voltages

 netVoltages (

  ("Vss_Int" (0.0))

  ("Vdd_1v8" (1.8 1.0))

  ("Vssa" (0.0))

  ("Vdd_3v3" (3.3))

  ("Vss" (0.0))

  ("Vdd_Int" (3.3 1.0))

 ;;; External Switchable Nets

 externalSwitchableNets nil

 ;;; Devices

 devices (nil

  cap (

   ("analogLib" "cap" nil)

  pfet (

   (nil "pmos*" nil)

   ("analogLib" "pmos*" nil)

   ("gpdk*" "pmos*" nil)

  nfet (

   (nil "nmos*" nil)

   ("analogLib" "nmos*" nil)

   ("gpdk*" "nmos*" nil)

  short (

   ("analogLib" "res" nil)

   ("analogLib" "rcwireload" nil

    (nil

     shortedTerminalMap  (("t1" "t2") ("t3" "t4" "t5"))

  diode (

   ("analogLib" "diode" nil

    (nil

     pTerm               "PLUS"

     nTerm               "MINUS"

 ;;; Transistor Terminal Names

 txTermTypeNames (nil

  substrate  "S BULK well SUB"

  bulk          "B BULK well SUB"

  emitter       "e E emitter"

  collector  "c C collector"

  source        "s S source SOURCE Source"

  drain         "d D drain DRAIN Drain"

  gate          "g G gate GATE Gate"

  base          "b B base BASE Base"

 ;;; Library Files

 libFiles (

  "./DESIGN1/LIBRTY/fast_vdd1v0_basicCells.lib"

  "./DESIGN1/LIBRTY/macro.lib"

  "./DESIGN1/TECHUPF/diode.upf"

  "./DESIGN1/TECHUPF/lshifter.upf"

  "./DESIGN1/TECHUPF/isolation.upf"

  "./DESIGN1/TECHUPF/pswitch.upf"

  "./DESIGN1/LIBRTY/macro.lib"

  "./DESIGN1/LIBRTY/VPMWS_ANA_OpAmp.lib"

 ;;; Text Files Specifying Library Files

 libInputFiles nil

 ;;;  Cell 1801 File Bindings

 cell1801Bindings nil

 ;;;  User Macro Cells

 userMacroCells nil

 ;;;  Reference Library-Cells

 refLibCells nil

 ;;; Supply Sets

 supplySets (

  (nil

   supplySetName   "SS_vdd3v3_vss"

   power              "Vdd_3v3"

   ground             "Vss"

  (nil

   supplySetName   "SS_vdd1v8_vss"

   power              "Vdd_1v8"

   ground             "Vss"

  (nil

   supplySetName   "SS_vddsw_vss"

   power              "Vdd_Int"

   ground             "Vss_Int"

 ;;; Power Domains

 powerDomains (

  (nil

   domainName              "PD_vddsw_vss"

   elements                "I4"

   primarySupplySet        "SS_vddsw_vss"

  (nil

   domainName              "PD_vdd3v3_vss"

   elements                "."

   primarySupplySet        "SS_vdd3v3_vss"

   includeScope            t

  (nil

   domainName              "PD_vdd1v8_vss"

   elements                "I0 I2"

   primarySupplySet        "SS_vdd1v8_vss"

 ;;; Port Attributes

 portAttributes nil

 ;;; Maximum number of similar violations to be reported

 maxSimilarViolations 1

 ;;; Use supplyStates

 useSupplyStates t

 ;;; Supply States

 supplyStates (

  ("SS1" ("Vss 0.000000" "Vdd_Int 3.300000" "Vdd_3v3 3.300000" "Vssa 0.000000" "Vdd_1v8 1.800000" "Vss_Int 0.000000"))

  ("SS2" ("Vss 0.000000" "Vdd_Int 3.300000" "Vdd_3v3 OFF" "Vssa 0.000000" "Vdd_1v8 1.800000" "Vss_Int 0.000000"))

 ;;; Input Voltage Tolerance Lower-Bound

 inputVoltageToleranceLowerBound -0.100000

 ;;; Input Voltage Tolerance Upper-Bound

 inputVoltageToleranceUpperBound 0.100000

 ;;; Input Ground Voltage Tolerance Lower-Bound

 inputGroundVoltageToleranceLowerBound -0.100000

 ;;; Input Ground Voltage Tolerance Upper-Bound

 inputGroundVoltageToleranceUpperBound 0.100000

 ;;; In-Design Checks Filter Patterns

 lprcFilters nil

 ;;; Missing Level-Shifter Check Severity

 missingLSCheckSeverity "error"

 ;;; Incompatible Level-Shifter Check Severity

 incompatibleLSCheckSeverity "error"

 ;;; Redundant Level-Shifter Check Severity

 redundantLSCheckSeverity "warning"

 ;;; Protected Level-Shifter Check Severity

 protectedLSCheckSeverity "info"

 ;;; Unprotected Level-Shifter Check Severity

 unprotectedLSCheckSeverity "error"

 ;;; Unreliable Level-Shifter Check Severity

 unreliableLSCheckSeverity "ignore"

 ;;; Floating Level-Shifter Check Severity

 floatingLSCheckSeverity "error"

 ;;; Always Enabled Level-Shifter Check Severity

 alwaysEnabledLSCheckSeverity "error"

 ;;; Unused Enable Level-Shifter Check Severity

 unusedEnableLSCheckSeverity "error"

 ;;; Missing Isolation Check Severity

 missingISOCheckSeverity "warning"

 ;;; Incompatible Isolation Check Severity

 incompatibleISOCheckSeverity "warning"

 ;;; Redundant Isolation Check Severity

 redundantISOCheckSeverity "warning"

 ;;; Incompatible Bulk Check Severity

 incompatibleBulkCheckSeverity "error"

 ;;; Report isolation violations for always-on-switched domain crossings

 reportOnOffISOViolations nil

 ;;; Check ports without any portAttributes definition in setup

 checkPortsWithoutAttributes nil

 ;;; Report violations for all net voltages

 reportLPRCViolationsForAllNetVoltages nil

 ;;; Prefixes for Supply Net netSet Props

 powerNetPropPrefix   "vdd"

 groundNetPropPrefix  "vss"

 pwellNetPropPrefix   "vdd_sub"

 nwellNetPropPrefix   "vss_sub"

 deeppwellNetPropPrefix "vdd_sub2"

 deepnwellNetPropPrefix "vss_sub2"

 ;;; Project MLDB Library Name

 projectMldbLibName ""

 ;;; Reference MLDB Library Names

 referenceMldbLibNames nil

 ;;; replaceExistingLibs

 replaceExistingLibs t

 ;;; Replicates missing driver_supply_set or receiver_supply_set for input, output ports respectively.

 replicateMissingDriverReceiverSupplySet nil

 ;;; Power Domain Name Prefix

 powerDomainNamePrefix "PD"

 ;;; Enable Automatic Creation of Power Domains

 autoCreatePowerDomains nil

 ;;; Consider signal type for detecting PG nets

 considerSignalType nil

 ;;; Set the mode (design/auto) for extraction

 extractionMode "design"

 ;;; Set how the PST/Power State are Created

 powerStateCriteria "Conservative"

 ;;; Set if All Off PST/Power Stated are Created

 includeAllOffStates nil

 ;;; Control printing of nets identified as supply nets

 printSupplyNetInfo nil

 ;;; Set if inout pins are allowed as LDO pins

 allowInoutLDOPins nil

 ;;; Set if inout pins are allowed as monitor pins

 allowInoutMonitorPins nil

 ;;; Delimiter for use in power intent objects like Supply Set Names

 delimiter "__"

 ;;; View Name list for hierarchy elaboration

 switchViewList "schematic symbol"

 ;;; Stack transistor device param names

 stackTransistorDeviceParamNames ""

 ;;; View Name list for pruning the hierarchy elaboration

 stopViewList "symbol"

 ;;; Set if the environment options are to be loaded

 loadEnvironmentOptions nil

 ;;; Set if the options not overridden by the user are to be updated

 pushUnmodifiedEnvOptions t

 ;;; Use anonymous supply set for non-annotated top level ports

 topPortsHaveAnonSupply t