proute_stripes
proute_stripes
-layers {s_layerName…}
-nets {s_netName…}
-net_width f_userunit
[ -set d_setObj | -instances {s_instName…} ]
[ -blockage {f_xlo f_ylo f_xhi f_yhi} ]
[ -direction {horizontal|vertical} ]
[ -max_length f_userunit ]
[ -max_width f_userunit ]
[ -min_length f_userunit ]
[ -min_length_to_rings f_userunit ]
[ -net_clearance f_userunit ]
[ -pin_clearance f_userunit ]
[ -observe_rectilinear_prBoundary [ true | false ] ]
[ -ignore_same_net_shape [ true | false ] ]
[ -routing_area
{{f_xlo f_ylo f_xhi f_yhi} | {f_x1 f_y1 f_x2 f_y2 f_x3 f_y3 … f_xn f_yn}}
[ -snap_to_core_ring [ true | false ] ]
| -use_design_boundary [ true | false ]
| -use_regions_on_scratch_layer i_scratchID ] ]
[ -x_step f_userunit | -y_step f_userunit ]
[ -bottom_offset f_userunit | -y_offset f_userunit ]
[ -left_offset f_userunit | -x_offset f_userunit ]
[ -all_term_types {core_ring | block_ring | stripes | cell_row_straps
| unknown} ]
[ -centerline [ true | false ] ]
[ -full_overlap [ true | false ] ]
[ -ignore_obstacles [ true | false ] | -ignore_purposes {s_purposeName…}]
[ -interior_stripes [ true | false ] ]
[ -interior_stripes_of_class1 [ true | false ] ]
[ -interior_stripes_of_class2 [ true | false ] ]
[ -interior_stripes_of_class3 [ true | false ] ]
[ -interior_stripes_of_class4 [ true | false ] ]
[ -interior_stripes_of_class5 [ true | false ] ]
[ -jog_stripes [ true | false ]
[ -max_wrong_way_jog_of_class1 f_userunit ]
[ -max_wrong_way_jog_of_class2 f_userunit ]
[ -max_wrong_way_jog_of_class3 f_userunit ]
[ -max_wrong_way_jog_of_class4 f_userunit ]
[ -max_wrong_way_jog_of_class5 f_userunit ]
[ -max_wrong_way_jog f_length ] ]
[ -max_wrong_way_ring_jog f_length ]
[ -max_full_overlap_jog f_length ] ]
[ -section_length f_userunit -section_step f_stepLength ]
[ -power_only [ true | false ] ]
[ -undoable [ true | false ] ]
[ -stop_at_boundary_of_class {s_className…}
[ -boundary_clearance {f_clearanceValue
| {f_leftValue f_bottomValue f_rightValue f_topValue}} ] ]
[ -stop_at_boundary_of_class1 {s_className…}
[ -boundary_clearance1 {f_clearanceValue
| {f_leftValue f_bottomValue f_rightValue f_topValue}} ] ]
[ -stop_at_boundary_of_class2 {s_className…}
[ -boundary_clearance2 {f_clearanceValue
| {f_leftValue f_bottomValue f_rightValue f_topValue}} ] ]
[ -stop_at_boundary_of_class3 {s_className…}
[ -boundary_clearance3 {f_clearanceValue
| {f_leftValue f_bottomValue f_rightValue f_topValue}} ] ]
[ -stop_at_boundary_of_class4 {s_className…}
[ -boundary_clearance4 {f_clearanceValue
| {f_leftValue f_bottomValue f_rightValue f_topValue}} ] ]
[ -stop_at_boundary_of_class5 {s_className…}
[ -boundary_clearance5 {f_clearanceValue
| {f_leftValue f_bottomValue f_rightValue f_topValue}} ] ]
[ -ignore_blockage_of_class {s_className…}]
[ -core_ring_layers {s_layerName …} | all]
[ -stop_at_rings [ true | false ] [ -ring_layers {s_layerName…} ]
[ -incomplete_rings [ true | false ] ]
| -class_applies_to_top_level_rings [ true | false ] ]
[ -class1 {s_className …} ]
[ -class2 {s_className …} ]
[ -class3 {s_className …} ]
[ -class4 {s_className …} ]
[ -class5 {s_className …} ]
[ -stop_at_rings_of_class1 {s_className…} [ -ring_layers1 {s_layerName…} ]
[ -incomplete_rings1 [ true | false ] ]
[ -ring_pin_prop_name1 s_propName -ring_pin_prop_value1 s_propValue ] ]
[ -stop_at_rings_of_class2 {s_className…} [ -ring_layers2 {s_layerName…} ]
[ -incomplete_rings2 [ true | false ] ]
[ -ring_pin_prop_name2 s_propName -ring_pin_prop_value2 s_propValue ] ]
[ -stop_at_rings_of_class3 {s_className…} [ -ring_layers3 {s_layerName…} ]
[ -incomplete_rings3 [ true | false ] ]
[ -ring_pin_prop_name3 s_propName -ring_pin_prop_value3 s_propValue ] ]
[ -stop_at_rings_of_class4 {s_className…} [ -ring_layers4 {s_layerName…} ]
[ -incomplete_rings4 [ true | false ] ]
[ -ring_pin_prop_name4 s_propName -ring_pin_prop_value4 s_propValue ] ]
[ -stop_at_rings_of_class5 {s_className…} [ -ring_layers5 {s_layerName…} ]
[ -incomplete_rings5 [ true | false ] ]
[ -ring_pin_prop_name5 s_propName -ring_pin_prop_value5 s_propValue ] ]
[ -silent [ true | false ] ]
[ -use_cellname_as_class [ true | false ] ]
[ -ring_extension_upper_layer f_userunit ]
[ -ring_extension_lower_layer f_userunit ]
[ -use_wsp [ true | false ] ]
[ -wsp_pullback_left f_userunit]
[ -wsp_pullback_right f_userunit]
[ -wsp_pullback_top f_userunit]
[ -wsp_pullback_bottom f_userunit]
[ -ignore_boundary_tracks [ true | false ] ]
Description
Adds net stripes at regular intervals. If more than one net is specified, the stripes are added in groups, in the order given, and repeated according to the stepsize.
Two methods are provided for placement of the stripes:
- Absolute Offset from Origin
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Relative Offset from Boundary
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For horizontal stripes, use
-bottom_offsetto indicate the y-axis distance from the bottom boundary (either the design’s bottom edge or f_ylo if-routing_areais given) to the lower edge of the first stripe. -
For vertical stripes, use
-left_offsetto indicate the x-axis distance from the left boundary (either the design’s left edge or f_xlo if-routing_areais given) to the left edge of the first stripe.

-
For horizontal stripes, use
The power router will not route on blockages. In addition, you can prevent routing on all layers of a given area, using the -blockage argument.
Class options let you control stripe truncation at block rings inside cell hierarchy. You can specify up to five macro cell classes and a corresponding list of ring layers for which the truncation applies. If a macro cell has a ctuPowerRouteClass property, then the value of that property can be listed in the *of_class* options.
Two mutually required arguments, -section_length and -section_step, let you create tandem stripe sections in a regular pattern.
Arguments
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Treats the given classes of macro block terminals on specified ring layers as this power type. |
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Prevents routing of stripes in this region. This allows you to create a hole in the stripes. |
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Specifies the y location of the first horizontal stripe relative to the bottom bounds (entire design or given by |
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Specifies the clearance for blocks of the class given by |
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Specifies the clearance for blocks of the class given by the |
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If |
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Stops strap extensions at top-level block rings around blocks whose class is specified in the “of class” arguments. |
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Specifies a list of classes of macro blocks that belong to classx for “of_classx” arguments. |
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By default, stripes are terminated at core rings using all core ring layers to determine the bounds. If |
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Specifies the routing direction for the stripes. By default, the preferred routing direction for the given layer is used. |
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When |
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Ignores the blockages in macro blocks that belong to a class in this list. |
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Restricts from creating the tracks on the boundary of a region. |
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When |
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Similar to |
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When |
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When |
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When |
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When |
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When |
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Specifies the maximum stripe width (overrides the |
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Specifies the maximum distance to jog in the wrong-way direction. Default is equal to the |
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(Applies only when |
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Specifies the maximum distance to jog in the wrong-way direction when stopping at rings. Default is equal to the |
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Specifies the minimum allowed stripe length. |
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Specifies the minimum length for stripes that stop at rings. |
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Specifies the spacing required between the power net stripes. |
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Specifies the total width for a stripe of each net routed. By default, each net stripe is one wire that is
If you specify a net width value that is greater than the |
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Specifies the nets to route. One or more nets can be given. When more than one net is given, the list order of the nets determines the placement of the stripes, with the first net on the leftmost stripe for vertical stripes, or on the bottommost stripe for horizontal stripes. |
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If |
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Specifies the clearance required between signal pins and the power nets. |
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If |
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Distance to extend stripe past inner edge of a ring segment on the metal layer below stripe. |
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Distance to extend stripe past inner edge of a ring segment on the metal layer above stripe. |
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Specifies the ring layers for |
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Used with |
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Used with |
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Specifies the outer boundary for the stripes as a rectangular boundary given by the lower left and upper right coordinates or as a rectilinear boundary given by a list of an even number of at least four (4) x-y coordinate pairs. Only stripes that fit entirely inside this area are drawn. If this argument is not given and core rings exist, the core rings become the bounds for the stripes. If this argument is not given and the core rings do not exist, the stripes will cover the entire design. |
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Breaks each logical stripe into tandem sections of this length. |
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Specifies the distance or pitch between tandem stripe sections. |
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Treats the prBoundary of the instances in the set as blockages. |
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When |
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(Used with |
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Stops stripe sections at the boundary of macro blocks that belong to a class in this list. Use |
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Stops strap extensions at the boundary of macro blocks that belong to a class in this list. Use |
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Stops stripes sections at top-level block rings and internal rings of blocks whose class is not specified in the * |
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Stops stripe sections at the internal block rings of macro blocks that belong to a class in the given list. |
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Permits this command to be undone. Default is the current setting for the |
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Allows specification of cellnames instead of class names for the |
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(Cannot be used with |
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(Cannot be used with |
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Creates stripes on the tracks from wsp regions instead of netwidth and regions provided. |
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Specifies the x location from the design origin to the first vertical stripe. |
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Specifies the y location from the design origin to the first horizontal stripe. |
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Specifies the y distance between sets of horizontal stripes. |
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Specifies pullback in the bottom direction by the value provided. The pullbacks are applied to vertical layers. |
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Specifies pullback in the left direction by the value provided. The pullbacks are applied to horizontal layers. |
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Specifies pullback in the right direction by the value provided. The pullbacks are applied to horizontal layers. |
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Specifies pullback in the top direction by the value provided. The pullbacks are applied to vertical layers. For example, on |
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Examples
The following example uses relative addressing for placing stripes in a region. Stripes on layer M6 are added for the VDD net with a width of 8 and spaced 12 apart, left edge-to-left edge. The stripes are vertical because that is the preferred direction for layer M6.
proute_stripes -layers M6 -net_width 8 -nets VDD -left_offset 0 -x_step 12 -routing_area {200 300 250 350 }

The next example creates stripe pairs of VDD and VSS on two layers. net_clearance is the spacing between the nets. The stripes are restricted to the routing_area, with the position of the bottommost and leftmost stripes given by absolute offsets (x_offset and y_offset) from the origin.
proute_stripes -nets {VDD VSS} -layers {met4 met5} -net_width 8 -net_clearance 3.5 -x_offset 1450 -y_offset 1450 -x_step 100 -y_step 100 -routing_area {1400 1400 1720 1720}

If the -routing_area argument is not given, the stripes are extended to the core ring, if it exists, or to the bounds of the design if there is no core ring.

The following command creates tandem stripe sections of VDD and VSS in a regular pattern.
proute_stripes -nets {VDD VSS} -layers met4 -net_width 8 -net_clearance 3 -x_step 100 -routing_area { 1000 1500 1450 1950} -section_length 40 -section_step 100

proute_stripes -use_wsp true -nets "vccr_cw vss_cw vcc1 vss1 vcc2 vss2" -layers Metal4 -centerline true -routing_area {0.000 0.000 10 10} -wsp_pullback_left 0.08
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