Product Documentation
Virtuoso Layout Suite XL: Connectivity Driven Editing User Guide
Product Version IC23.1, November 2023

Pins and Pin Names in Layout XL

For connectivity assignment tracing and cross-probing to work correctly in Layout XL, the pins and pin names in the layout cellview of a device must match those in the corresponding schematic symbol.

Extra Pins in the Symbol or Layout Views

Layout XL cannot maintain connectivity for any extra pins in the symbol view because there is no corresponding pin for the device in the layout view.

Conversely, Layout XL maintains connectivity for extra pins whose names are global nets (for example, vdd!) in the layout view. It also maintains connectivity for any extra pins in the layout that have their connectivity defined by inherited connections. The inherited connection can be defined relative to the layout instance itself or relative to the schematic hierarchy that ends with the schematic instance corresponding to that layout instance.

The look-up order used by Layout XL to determine the net to connect to an extra pin is:

  1. Inherited net expression on the layout pin.
  2. Global net — global attribute or ! at the end of the net name.
  3. Property named sub, sub_inh, or bn on the layout master.
    • Layout XL uses the value of the property as the substrate net name and connects the extra terminal to that net.
      Cadence recommends not to place pins where you do not want to make a connection. For example, on a polysilicon layer that covers the gate area of a FET.

Related Topics

Adding a Pin

External Connections

You can also define pins to be connected externally to the design.

The commands in the Connectivity – Pins submenu let you connect pins in four different ways.

Related Topics

Using Connectivity

permuteRule Property

Device Abutment


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