Generating Parameterized Layout Cells (VPLGen)

VPLGens are Cadence-supported hierarchical Pcells that require no SKILL coding and can be edited using all the standard Virtuoso tools, including Layout XL, floorplanner, automatic placers, routers, and so on.

You can use VPLGens when you need a hierarchical Pcell but there are no resources available to create the required SKILL code, or in any situation where you want a single schematic symbol to create a range of similar but slightly different standard layouts and you expect to re-use the same set of inherited parameters on each.

For example, you want to accelerate the process of creating a standard cell library of inverters, nand gates, and so on. For a single schematic pmos or nmos cell, you might want to specify different numbers of devices (mfactors) or different widths, lengths, and numbers of fingers.

You want to specify different layout variants for a single schematic cell, for example, with different routing to connect the devices slightly differently. You can add a (non-inherited) routing parameter to the schematic instance and use this to switch between the different variants of the instance in the layout.

In the absence of schematic instances, VPLGens can also be created for symbol views.

You specify that a schematic cell is to be implemented as a VPLGen in the Configure Physical Hierarchy window, and use Layout XL to generate an instance of that schematic cell in the layout and edit that instance to create a core layout that meets your specifications.

The core layout can then be saved either in your design library or a separate library and re-used later in other designs using the same process node.

You can optionally set the core layout to be the default layout for a particular schematic cell. Whenever you generate an instance for that cell, Layout XL copies the default layout into the design as a VPLGen Pcell instance, which you can use as a starting point for further editing. If the default layout does not meet your requirements, you can map the VPLGen Pcell instance to a different layout in your design library and use that instead.

If you have a Cadence Support portal account, you can download the Virtuoso Parameterized Layout Generators VPLGen rapid adoption kit that comprises a workshop database and a guided lab manual to help you experience the productivity gain from using VPLGens for creating reusable layouts in a test environment.

This section describes the Virtuoso parameterized layout generator (VPLGen) functionality, which lets you create and re-use predefined layouts for schematic instances that differ only in terms of their inherited parameter values.

VPLGen Environment Variables

The VPLGen functionality is supported by the following environment variables:

VPLGen SKILL Functions

The VPLGen functionality is supported by the following SKILL functions:

This section covers the following topics:

Virtuoso Layout Suite XL: Connectivity Driven Editing User Guide
Product Version IC23.1, November 2023