createImplicitBusTerminals

layoutXL createImplicitBusTerminals boolean { t | nil }

Description

Creates, checks, and updates implicit bus terminals in the layout cellview, based upon the explicit bus terminals in the schematic cellview. This avoids the need for running VerilogAnnotate to annotate the bus terminal and bus bit order (ascending or descending) information into the layout view. In addition, it enhances the interoperability of layout cellviews with the Innovus designs. The bus connectivity is created in the layout view as "implicit" objects so that they are not visible to other parts of Virtuoso. For example, the implicit bus terminals generated by Layout XL do not show up in the list of terminals associated with the layout cellview when accessed through SKILL.

Layout XL also sets the isInterface flag on the implicit bus terminal to true and that on the explicit bit terminals to false. This maintains the information as in the original schematic design.

The createImplicitBusTerminals environment variable also controls the annotation of bus terminals into layout cellviews generated by the Generate Physical Hierarchy command in Virtuoso GXL".

The default is t.

GUI Equivalent (Only supported by GFS)

Command:	Options – Connectivity (Generation tab)
Field:	Create implicit bus terminals (Connectivity Form)

Examples

envGetVal("layoutXL" "createImplicitBusTerminals")

envSetVal("layoutXL" "createImplicitBusTerminals" 'boolean t)

envSetVal("layoutXL" "createImplicitBusTerminals" 'boolean nil)

Related Topics

Soft Block Mode

Design Check Against Source

Generation

List of Layout XL Environment Variables

Setting Environment Variables

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