Commercial mixed-signal simulation solutions – like the Xcelium simulator with the mixed-signal option and Spectre AMS Designer (AMS Designer) simulator – are available to manage multiple power supply domains, bidirectional interface connections, varieties of analog solving algorithms. Mixed-signal extensions to the standard behavioral languages (Verilog-AMS and VHDL-AMS) provide flexible modeling capabilities. Given that, mixed-signal simulation in itself can be considered as a solved problem.
However, simulation is only the enabling part for the verification process. The verification environments are still separated in an analog-driven flow or a digital-centric methodology as described above. The choice of the right level of design abstraction is especially important when moving to mixed-signal simulation.
Mixed-signal simulation is used mainly by the analog design team. Consequently, the use model is aligned with the analog workflow. AMS Designer is integrated in the ADE use model. It can read design information from the dfII database as well as file-based descriptions.
Significant demand for mixed-signal simulation within the digital use model has been visible over the last couple of years. AMS Designer’s command line use model fulfills these requirements. A simulation can be set up and started easily from the command line. This enables a straightforward integration into the digital-centric verification flow as well as all the flexibility needed for the mixed-signal simulation.
The analog content in many design flows is represented only as Verilog-AMS or SPICE-level netlists. The goal was to make the flow as simple as possible, however, compared to a pure digital simulation, some additional information also needs to be provided such as.
- Settings for the analog solver
- Including analog (SPICE) content
- Configure the design parts that should be replaced by analog blocks
- Define the Connect Modules (CM) to connect analog and digital signals
- Define the port mapping information between SPICE and Verilog
Analog verification is based on the idea of simulating the circuit with a given input stimulus and observing the correct output behavior. In most cases, this process is still based on manual waveform inspections because:
- Necessary measurements and calculations on analog waveforms are sometimes hard to formulate in a mathematical way while a manual check is very easy and fast for an experienced designer.
- Waveform inspection is a major part of the analog workflow.
- Analog design is not very formalized and still relies heavily on expert knowledge. This implies that there are a significant amount of implicit assumptions besides the specification that need to be taken into account.
The following are some guidelines to achieve the best performance (run-time) in AMS simulation:
- Avoid current probes with wildcards and use specific current probes. Alternatively, consider using dynamic check features for current/power analysis and debug, especially for multiple current waveforms for test cases focusing on
low-power-mode current consumption, IDDQ, reliability, etc. - Consider using analog assertions and self-checking mechanisms as much as possible.
- Use the Save and Restart feature in AMS. See Using the Save-and-Restart Feature.
- Use an appropriate envelope as a stimulus instead of the full RF signal for RF TX FE simulation.
Even though a complete replacement of manual waveform inspection in analog design may not be realistic today, it is relatively easy to automate the straightforward checks in the analog working environment. The Virtuoso Analog Design Environment (ADE) is a very common workplace for analog designs. For more information, see the Virtuoso Analog Design Environment XL User Guide.