Digital verification flow includes important intersections with analog, which adds challenges when bringing the two together for mixed-signal verification. A simplified view of the digital verification flow as it applies to implementation is as follows:
- Functional verification through RTL simulation.
- Equivalence checking of RTL and gate-level.
- Static timing analysis throughout the design.
Functional verification is the most critical and costly verification step at a relatively high level of abstraction. Equivalence checking provides the verification against the synthesized gate design and other checks for structural, functional, and electrical integrity. The timing of the final place and route implemented physical design is checked by the static timing analysis step.
Equivalence checking generates mathematical models of the two different circuit representations in order to determine the equivalence. There are some theoretical approaches to apply those techniques to analog design as well, but in general, this step is not related to mixed-signal verification.
Since static timing analysis is only applicable in context with a reference clock, it is not directly useful for analog blocks. However, it is important to consider analog parts when integrating the analog IP into an SoC, since the analog block might be part of a critical path through the design. This situation is solved either by running detailed performance simulations using mixed-signal tools to check the timing or by creating a timing model for the analog blocks and using this model during standard static timing analysis. The method employed here is leveraging the analog design environment setting up an automatic regression suite for each analog architecture and then having the analog environment generate the input data for the timing model.
The challenge of digital functional verification comes down to answering the question of whether or not enough simulations have been run and all corner cases have been covered. Only additional measures, such as code coverage, assertion coverage, and functional coverage provide this information and enable an easy assessment of the current verification status. Finally, reuse and automation are much better supported in modern verification techniques (see below).
Verification Plan and Metric-Driven Verification
The verification plan is refined, modified, and enhanced during the design and verification process. This is because the design, spec, and experiences are changing during the design phase. Clearly defined verification goals are very helpful for the whole verification process, even if the goals are not formally written down in a verification plan.
Advanced verification techniques have been developed and introduced in today’s digital design flows to overcome the limitations and productivity restrictions. The prediction of verification quality is a major improvement in the state of the art verification methods. The main components of these verification techniques are:
- Automated random stimulus generation
- Automated self-checking (assertions and reference models)
- Coverage measurements and tracking
- Adding formal methods into the verification flow
The design under test (DUT) is stimulated with some input data, simulated, and the simulation results are stored. There are two important tasks:
- Generation of input stimuli
- Checking the results against expectations
A third task is a functional coverage to measure which verification goals have been achieved during simulation.
Metric-Driven Verification and Advanced Testbench
A metric-driven verification flow assembles the factors of digital verification flow. The simulation results are automatically checked and problems are being reported. An automatic stimuli generator creates tests on a random basis within given constraints. Additionally, you may have some tests that are pre-defined and need to be run (directed tests) to reach certain corner cases. The advanced testbench takes care of these different simulation scenarios. The testbench is typically written in e or SystemVerilog; and, also in SystemC, Verilog, or VHDL.