SystemVerilog Interconnects

SystemVerilog (SV) interconnect nets are specified using the keyword interconnect and can be used only in net_lvalue port expressions. These are also called explicit interconnects. In addition, there are interconnect nets, also called implicit interconnects, that are declared as wires but through analysis, the elaborator determines whether they should be treated as interconnect nets. Implicit interconnect nets are not declared using the interconnect keyword. SV supports both types of interconnect nets.

An implicit interconnect is considered an interconnect net, if it meets all of the below criteria:

• The net is declared as wire, tri, wand, triand, wor, or trior
• The net is used only in net_lvalue port expressions
• The net is either singular or a packed/unpacked array with a single dimension
• The net is used in concatenation expressions as actual or formal of a non-collapsible port association
• The net does not connect to a variable or expression with any of the following data types:
  • string
  • event
  • C Handle
  • unpacked struct that is not supported in the nettype declaration

In general, explicit interconnects can only be connected to nets. However, they can be connected to non-nets under the following conditions:

• If an interconnect connects to both non-nets and nets, the nettype of the interconnect will be the nettype of its net connections
• If all its connections (both net and non-net) do not have assignment-compatible datatype, an error is generated
• If its net connections do not have an equivalent nettype, an error is generated
• If an interconnect connects only to non-nets:
  • If the datatypes of all the non-net connections are not assignment-compatible, an error is generated
  • If all the non-nets have real datatype, the nettype of the interconnect is the built-in real nettype with the resolution CDS_res_wreal1driver
  • If all the non-nets have assignment-compatible non-real datatype, the nettype of the interconnect is an implied unresolved nettype with the datatype of the non-nets
  • If the non-nets have non-equivalent datatypes that are assignment-compatible, one of the datatypes is chosen for the implied unresolved nettype

Explicit interconnects are supported in the AMS CPF flow. For explicit interconnects, the following is supported:

• Power domain information on the interconnect net
• Creation of boundary port information on the interconnect net
• Power-smart IE (LPS IE) connections to the interconnect net
• Power state propagation on the mixed-signal boundary

Port Connection Rules

A singular interconnect can connect to any of the following:

• Singular net of user-defined nettype
• Scalar electrical net
• Singular wreal
• Singular built-in logic net

Connection of a singular interconnect to an array port, or an array port to a singular interconnect is governed by the following rules:

• If an interconnect array is connected to an SV array net of user-defined nettype, both upper and lower port expressions must have the same number of elements. You can use the xmelab/xrun option -nettype_port_relax to make the upper and lower port expressions have different number of elements.
• If an interconnect array is connected to a wreal array, the upper and lower port expressions may have different numbers of elements.
• If an interconnect array is connected to an electrical bus, the upper and lower port expressions may have different numbers of elements.
• If an interconnect array is connected to a packed built-in logic net array or structure, the upper and lower port expressions may have different numbers of elements.
• If an interconnect array is connected to an unpacked built-in logic net array, both upper and lower port expressions must have the same number of elements.
• An interconnect array cannot be connected to an unpacked built-in logic net structure.
• Power domain voltage check on mixed-signal boundary.