Connect Modules for SV-RNM Connections

• Built-In EE Package Connect Modules for SV-UDN to Electrical Connections/Connect Modules for SystemVerilog User Defined Nettype (SV-UDN) to Electrical Connections
• DMS IEs for UDN-UDN, UDN-Logic, and UDN-Real Connections/SV-AMS Connect Modules for UDN-UDN, UDN-Logic, and UDN-Real Connections

Connect Modules for SystemVerilog User Defined Nettype (SV-UDN) to Electrical Connections

You can connect a design that has SystemVerilog user-defined nettype (UDN) to electrical net connections by using the built-in or user-defined UDN to electrical bidirectional connect modules. This enables a SystemVerilog Real Numbered Model UDN and a Verilog-AMS (or SPICE/Spectre) electrical port connection on a mixed-signal net design.

To set up a SystemVerilog UDN-Electrical connection, you can do the following:

• Use the built-in nettype (EEnet) declared in the EE_pkg.sv package file to connect electrical ports (Verilog-AMS or SPICE/Spectre). These connections are done by inserting built-in Connect Modules (EEnet_2_E.svams, E_2_EEnet.svams, EEnet_to_E_bidir.svams). For more information, see Using the Built-In EE Package Connect Modules.
• Create custom user-defined nettype (UDN) with resolution function and custom Connect Modules to insert between custom UDN and electrical connections. For more information, see Using Custom User-Defined Nettype and Connect Modules.

SV-AMS Connect Modules for UDNUDN, UDN-Logic, and UDN-Real Connections

You can enable automatic insertion of SV-AMS connect modules for designs where both port connections are discrete nettypes including wire, SV wreal, and UDN such as:

• UDN (User Defined Nettype) to another UDN
• SV real nets (Built-in wreal or real UDNs) to logic nets
• UDN to a logic wire
• UDN to real nets (built-in VAMS/SVwreal nets or real UDNs)

The direction of the connect module is determined by the direction of the port that is declared across which it is inserted (input, output, or inout). Both the highcon and lowcon of the port must be nets, and the port must be collapsible for a connect module to be inserted.

At elaboration time, when the tool detects port connections, where both the upper and lower connected nets have different nettype, it inserts the custom SV-AMS connect modules with the correct parameterization.

To insert custom SV-AMS connect modules, you must specify the -rnm_dmsie option in the xrun command-line along with the -custom_udn_cr option and other required files such as the amscf.scs file, the SystemVerilog file (.sv), where the SystemVerilog block/structural netlists are defined, and the SystemVerilog-AMS (.svams) file that contains the connect module descriptions.

You can provide only UDN to UDN/Logic/Real connect modules. For DMS SV-RNM designs that do not use ie card and amsd block, and do not have a spectre *.scs file, you can specify the tool to automatically create ie card with the default vsup=1.8 by using the -auto_config_svams_ie option with the -rnm_dmsie option.