Wreal Coercion

During the elaboration phase, the connectivity of a mixed-signal design is computed. This also involves determining and attaching types, such as logic type and electrical type to interconnects (wires). The Verilog-AMS LRM only allows wreal ports and nets to connect to wires. In this case, the wires get resolved to the type wreal. This process is called coercion to wreal (wreal coercion).

When a wire/interconnect is connected to a net of the type wreal, SV real, or VHDL real, it is coerced to wreal as well. Such coercion occurs across multiple hierarchical levels. The coercion process allows a seamless connection of devices without worrying about the interconnects and their types. This offers tremendous value in terms of model portability across various design configurations. In a different configuration, interconnect might be used to connect electrical ports – this works seamlessly without any change in the source code.

The following example illustrates the wreal coercion function:

`include "disciplines.vams"

module top();
  wire w;
  sub1 I1 (w);
  sub2 I2 (w);
endmodule

module sub1(foo);
  output foo;
  source I1 (foo);
endmodule

module sub2(foo);
  input foo;
  sink I3 (foo);
endmodule

Some levels of hierarchy and the connection between the blocks are implemented using wires. Note that we have not defined any discipline or type for the wires. This is essential to give the elaborator the flexibility to choose the appropriate wire type. The following example illustrated how to use electrical definitions for the source and sink modules:

`include "disciplines.vams"

module source (r);
  output r;
  electrical r;
  analog begin
    V(r) <+ sin($abstime * 1e4);
    $bound_step(1e-5); // limit the step size
  end

endmodule // send

module sink (r);
  input r;
  electrical r;

  analog begin
    $display(" voltage = %f", V(r));
  end
endmodule

The entire wire hierarchy in the three top-level modules becomes electrical due to the connection of the wires to the electrical ports. Using exactly the same top-level hierarchy with different leaf-level blocks results in different wire type and discipline assignment.

`include "disciplines.vams"

module source(r);
  output r;
  wreal r;
  real realnumber;
  initial begin
    #1 realnumber = `wrealXState;
    #1 realnumber = `wrealZState;
    #1 realnumber = 2.2;
    #1 realnumber = 1.1;
    #1 $stop;
end
assign r = realnumber;
endmodule // send

module sink (r);
  input r;
  wreal r;
  always @(r) begin
    $display(" real value = %f", r);
  end
endmodule

In this case, the top-level wires are coerced to a wreal wire type. Thus, the coercion mechanism enables a straightforward reuse of testbench and sub-level hierarchies even if leaf-level blocks are swapped out by wreal blocks. Explicit definitions of wreal wire type in the upper levels of the hierarchy are not necessary.

Related Topics

• Advanced Wreal Modeling Features