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This chapter describes how to perform vector checks and apply stimuli according to digital vectors using the Virtuoso® UltraSim™ simulator. To process digital vector file formats, the following statement needs to be specified in the netlist file:
Note: A period (.) is required when using SPICE language syntax (for example, .vec).
HLCheck is a special flag that you need to set to generate the vector output check for H and L states of input signals. Bidirectional and output signals always check H and L states and are unaffected by the HLCheck flag. Normally, you do not need to use the HLCheck flag unless it is necessary to check if input signals are shorted in the netlist file. The output resistance of H and L states for input signals can be specified by the hlz statement.
Each vec card can specify only one vector file. If a netlist file needs to include multiple vector files, multiple vec cards can be used. For example, if a netlist file needs to include three vector files, then it needs to use three vec cards.
Card 1: vec_include "file1.vec"
Card 2: vec_include "file2.vec"
Card 3: vec_include "file3.vec"
The Virtuoso UltraSim simulator handles the vector file content as case insensitive, except when called in Spectre® mode. For Spectre mode, use the -spectre option or input file name extension *.scs.
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Special flag which turns on checking for the H and L states for input signals (default = 0) |
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Note: The autostop argument can also be used when loading .vcd and .evcd files. For more information about these files, see the Processing the Value Change Dump File section in the Verilog Value Change Dump Stimuli chapter. |
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Specifies whether vector file content is considered case sensitive or insensitive. By default, the Virtuoso UltraSim simulator determines case sensitivity based on the Spectre/SPICE mode used. When running in Spectre mode (*.scs file extension or -spectre), the vector file content is treated as case sensitive. In SPICE mode, the content is case insensitive. |
vec_include "vec1.vec" autostop=true
tells the Virtuoso UltraSim simulator to replace the end time with the time from the vec1.vec file (that is, the time from the vec1.vec file is used as the transient simulation end time).
The digital vector file is described in detail in the following sections:
A comment line begins with a semicolon `(;).
A continuous line is indicated by a plus sign `(+).
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For a long identifier (for example, a 1280-bit vector bus) that cannot fit on a single line, use the forward slash \ sign after the last bit. Do not use a space between the last bit and the \ sign. Put a space in front of the continuous vector or use a + sign. If you use a + sign, the continuous vector is treated as another vector bus. |
A signal mask can be used to specify the effective range of the current statement in a vector file (statement applies to specific signals). The Virtuoso UltraSim simulator matches the signals according to the signal definition order in the radix, vname, and io statements. For the corresponding signal, a value of 1 indicates the statement is valid and a value of 0 indicates the statement is ignored. Based on the size of the vector specified in the radix statement, the signal mask value can range from 0 to 1 for 1bit, 0 to 3 for 2bit, 0 to 7 for 3bit, and 0 to 9 or A to F for 4bit.
The above example contains a single bit vector EN, and multiple bit vectors A, B, P. The mapping between the vectors and analog signals are as follows:
When you specify a mask value to a 2-bit vector it expands as follows:
In above example, the default value of vih 2.5V. With masks, vih is set to 1.8V for signal EN, and 3.3V for A1 A0. Other signals use the default value.
The chk_window statement specifies a window for vector checking. The Virtuoso UltraSim simulator only checks the signal states within this window. The signal states outside the window are ignored. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all output vectors. The first parameter is start_time and defines the window, which starts at time vec_time-start_time. The second parameter is end_time and defines the window, which ends at time vec_time+end_time. In this example, the start_time is negative which means the checking window starts 1ns after vector time.
For more information about the statements used in this example, refer to "Vector Patterns" and "Signal Characteristics".
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If the radix of the vector is larger than 1, the name of this vector specified in vname must be indexed as [msb:lsb] or [lsb:msb]. If the radix is 4, the vname can use names such as name[3:0] and name[0:3]. |
contains three vectors: Two 2-bit vectors and one 4-bit vector.
Note: The examples presented in the rest of this chapter follow this format.
also contains three vectors, two 2-bit vectors and one 4-bit vector, but in a different format.
The io statement defines the type of vector. It can be the i (input), o (output), or b (bidirectional) type. If this statement is specified more than once, the last value is used.
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Use the enable statement to specify the control signal for the bidirectional vector (b). If this specified control signal is not found, the Virtuoso UltraSim simulator issues an error. |
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If the control signal of the bidirectional vector is not specified by the enable statement, the Virtuoso UltraSim simulator treats it as an input signal. |
The first and second vectors are input vectors, and the third vector is an output vector.
The vname statement assigns a name to each vector. For a single bit vector, it can have the following naming format: Va, Va[0:0], or Va[[0:0]]. For multiple bit vectors, the naming formats include: Va[2:0], Va[[2:0]], Va[0:2], or Va[[0:2]]. Each naming format is given a different resulting name. If this statement is specified more than once, the last value is used.
Hierarchical signal names are also supported by vname. That is, you can apply vector stimuli or perform a vector check on the internal signals of instances. When mapping hierarchical signal names, the default delimiter is a period (.). You can change the value of the delimiter using the hier_delimiter option in the analog netlist file. The hier statement can be used to enable or disable this option.
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Internal signals Va0, Va1, and Va2 of instance X1 |
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Internal signals Va[0], Va[1], and Va[2] of instance TOP.X1 |
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If the radix of the vector is larger than 1, the name of the vector specified in vname must be indexed as [msb:lsb] or [lsb:msb]. If radix is 4, vname can use names such as name[3:0] and name[0:3]. |
vname va[1:0] vb[[1:0]] vc[[0:3]]
tells the Virtuoso UltraSim simulator that the voltage sources in the first vector are named va1 and va0. Voltage sources in the second vector are connected to vb[1] and vb[0]. The third vector has voltage sources with the names vc[0], vc[1], vc[2], and vc[3].
vname X1.va[1:0] X2.vb[[1:0]] X1.X3.vc<[0:3]>
tells the simulator the voltage sources in the first vector are mapped to internal signals va1 and va0 of instance X1. Voltage sources in the second vector are connected to v[1] and vb[0] of instance X2. The third vector defines the output vector check for signals vc<0>, vc<1>, vc<2>, and vc<3> of instance X1.X3.
This option is used to specify whether or not the hierarchical signal name mapping feature is enabled. If hier is set to 0, the hierarchical delimiter (for example, signal period or .) is considered to be part of the signal name. The default value is 1 (hierarchical signal name mapping enabled). If this statement is specified more than once, the last value is used.
tells the Virtuoso UltraSim simulator to connect the voltage sources with the X1.va1 and X1.va0 signals located in the top level of the analog netlist file.
Sets the time unit for all time related variables. The time unit can be one of the following: fs (femto-second), ps (pico-second), ns (nano-second), us (micro-second), and ms (milli-second). The default time unit is 1 ns. If this statement is specified more than once, the last value is used.
The chk_ignore statement specifies a window for ignoring output vector checks. A mask can be provided to specify which vector and bit to apply. If the mask is not specified, the setting applies to all output vectors. The start_time and end_time arguments must be specified. To define multiple time windows for ignoring output vector checks, use multiple chk_ignore statements.
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Defines the start time for the window used to ignore the output vector checks (use tunit to define the start_time units). |
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Defines the end time for the window used to ignore the output vector checks (use tunit to define the end_time units). You can use end_time=-1 to ignore the entire transient time. |
chk_ignore 0 100 0F30 ; 0F30 is a signal mask
chk_ignore 0 -1 F000 ; F000 is a signal mask
tells the Virtuoso UltraSim simulator to ignore the output vector check for signals specified by the mask 0F30 in the time windows 0 ns to 100 ns and 300 ns to 500 ns, and to ignore the entire transient time for the signals specified by the mask F000.
The chk_window statement specifies a window for vector checking. The Virtuoso UltraSim simulator only checks the signal states within this window. The signal states outside the window are ignored. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all output vectors. The checks occur at every time point specified in the vector file or as defined by the period and first arguments.
Setting the period argument activates periodic window checking. If period is not defined, the first argument is ignored by the simulator.
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To activate periodic window checking, you need to include the "period=" and "first=" keywords. |
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Parameters and expressions are supported for the start_time, end_time, period, and first arguments (see "Examples" for more information about parameters and expressions syntax). |
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Defines the window start time at which the window starts at time vec_time-start_time. If the period argument is defined, vec_time is the first time point defined by the first argument, and the vector checks are repeated according to the value of period. If the period argument is not defined, vec_time is the time point defined in the vector file. |
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Defines the window end time at which the window ends at time vec_time+end_time. |
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steady = 0 | 1 |
Can be set to 0 or 1. If set to 0, then the vector check passes as long as the signal has reached the desired state once. If set to 1, then the signal remains in the desired state for the entire window period to pass the vector check. |
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Activates periodic window checking and defines its time period. |
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Defines the first check point for periodic window checking (only valid when the period argument is also defined). |
tells the Virtuoso UltraSim simulator to set the steady state to 0, so the waveform passes the vector check (see Figure 11-1 ).
Figure 11-1 Vector Check with chk_window Steady State Set to 0
tells the simulator to set the steady state to 1, which means the signal needs to stay at state 1 for the whole window period to pass the vector check, as shown in Figure 11-2. If the signal is as shown in Figure 11-1 , the vector check fails.
Figure 11-2 Vector Check with chk_window Steady State Set to 1
chk_window -10 30 1 period=100 first=5 0 0 1 0
tells the simulator to activate periodic window check for signal q. The vector check points start at 50 ns and repeat every 1 us.
chk_window -10 30 1 first=5 0 0 1 0
tells the simulator to ignore the first argument because a valid period argument has not been specified.
param mystartt=1.5 mystopt='(myfadd(mystartt, 50.5)'
tells the simulator to set the steady state to 1, the start time for chk_window to 1.5 ns, and the end time to 52 n (this example shows the chk_window parameters and expressions syntax).
The enable statement connects the enable signal, or enable signal expression, to the bidirectional vector. The resulting value 1 (H) enables the output signal. The controlled bidirectional signal is regarded as an input for other values.
The enable signal can be used in a vector or an analog netlist file. When an enable signal is used in an analog netlist file, it can also be defined as an output signal for a vector check or only used as an enable signal. The avoh and avol statements can be used to define the logic high and low voltage thresholds for the analog signal.
Note: The enable signal cannot be defined as a bidirectional signal.
Bit-wise logic operators are supported in an enable signal expression: & (AND), | (OR), ^ (XOR), and ~ (NOT). Additional operators can be created using a combination of the supported operators. The order of processing for the logic operators is NOT > AND > OR, XOR (OR and XOR are processed at the same time). You can use parentheses () around the operators to change the processing order.
Note: You need to use single quotation marks `' for enable signal expressions.
tells the Virtuoso UltraSim simulator to set en as the enable signal for bi, and when en is in 1 (or H) state, bi becomes the output signal. When en is in 0 (or L, X, U) state, bi changes to the input signal. When en is in Z state, the bi (input and output) signal also changes to Z state.
tells the simulator to set en as the enable signal for bi. Unlike the first example, this enable signal name contains a ~ sign, which reverses the state to control the bidirectional signal. Now when the enable signal is in 1 (or H) state, the bi becomes an input signal.
enable `(ana_en1 | X1.ana_en2) & out' 1 0 0
tells the Virtuoso UltraSim simulator that the ana_en1 and X1.ana_en2 enable signals originate in the analog netlist file, and X1.ana_en2 is a hierarchical signal. Although the out signal is used as an enable signal, the simulator still performs a vector check.
The period statement is used to specify the time interval for tabular data, so that the absolute time is not needed.
If period is not specified, then the absolute time must be specified in the tabular data. If it is specified more than once, the last value is used.
Note: In the following examples for time-related statements, the time unit is 1 ns if the statement is not specified with tunit.
Note: The Virtuoso UltraSim simulator checks whether the values of the trise, tfall, and slope statements are reasonable (warning message is issued when the defined value is too small or large).
The idelay statement specifies the delay time for the corresponding input signal. If a bidirectional signal is specified, this applies only to the input stage of the bidirectional signal. The default value is 0.0, if idelay or tdelay is not set.
tells the Virtuoso UltraSim simulator to delay all input signals by 5 ns, whereas
tells the simulator to advance all input signals by 5 ns.
The odelay statement specifies the time delay for the corresponding output signal. If a bidirectional signal is specified, this applies only to the output stage of the bidirectional signal. The default value is 0.0, if odelay or tdelay is not set.
tells the Virtuoso UltraSim simulator to delay all output signals by 5 ns, whereas
tells the simulator to advance all output signals by 5 ns.
The tdelay statement specifies the delay time for corresponding vectors. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all vectors (input, output, and bidirectional).
If tdelay is not specified, the default value is 0.0. If this statement is specified more than once, the last value is used for the active mask. This statement can also overrule the value previously set by the idelay or odelay statements.
tells the Virtuoso UltraSim simulator to advance all signals by 5 ns.
tells the simulator to advance all signals, specified with a mask, by 5.5 ns.
The slope statement sets the input vectors rise and fall time. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
If this statement is not specified, then the default value of 0.1 ns is used. If this statement is specified more than once, the last value is used for the active mask. This statement can also overrule the value previously set by the trise or tfall statements.
vname va[1:0] vb[[1:0]] vc[[0:3]]
The least significant bit, va0, of the first input vector and the two bits, vb[1] and vb[0], of the second input vector have a trise and tfall of 0.025 ns. The third vector is an output vector (specified in the io statement), so it is not affected by the slope statement.
The tfall statement specifies the falling time of the input vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
The value from the slope statement is used, if tfall is not specified. If this statement is specified more than once, the last value is used for the active mask. This statement can also overrule the value previously set by the slope statement.
tells the Virtuoso UltraSim simulator that all input vectors have a fall time of 0.05 ns.
vname va[1:0] vb[[1:0]] vc[[0:3]]
the most significant bit, vb[1], of the second input vector has a fall time of 0.1 ns. The fall time of vb[0] and other input vectors remains the same.
The trise statement specifies the rise time of the input vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
If trise is not specified, the value from the slope statement is used. If this statement is specified more than once, the last value is used for the active mask. This statement can also overrule the value previously set by the slope statement.
tells the Virtuoso UltraSim simulator that all input vectors have a rise time of 0.1 ns.
vname va[1:0] vb[[1:0]] vc[[0:3]]
the two bits of the second input vector has a rise time of 0.1 ns and the trise of the other input vector remains the same.
The vih statement specifies the logic high voltage of the input vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
If vih is not specified, the default voltage is 3.3. If this statement is specified more than once, the last value is used for the active mask.
The vil statement specifies the logic low voltage of the input vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
If vil is not specified, the default voltage is 0.0. If this statement is specified more than once, the last value is used for the active mask.
The voh statement specifies the logic high voltage of the output vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all output vectors.
If voh is not specified, the default voltage is 3.3. If this statement is specified more than once, the last value is used for the active mask.
The vol statement specifies the logic low voltage of the output vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all output vectors.
If vol is not specified, the default voltage is 0.0. If this statement is specified more than once, the last value is used for the active mask.
The avoh statement specifies the logic high voltage of the signal from the analog netlist file, which is not defined in the radix, vname, or io statements. You can provide signal names to specify the valid scope for avoh (wildcards are supported). A period (. ) can be used as the hierarchical delimiter to specify the hierarchical signal. If a signal name is not used, the setting applies to all analog signals used in the vector file.
For more information about wildcards, see "Wildcard Rules".
tells the Virtuoso UltraSim simulator that analog signals ana_en* and X1.Enanble have a logic high voltage of 1.0.
The avol statement specifies the logic low voltage of the signal from the analog netlist file, which is not defined in the radix, vname or io statements. You can provide signal names to specify the valid scope for avol (wildcards are supported). A period (.) can be used as the hierarchical delimiter to specify the hierarchical signal. If a signal name is not used, the setting applies to all analog signals used in the vector file.
For more information about wildcards, see "Wildcard Rules".
tells the Virtuoso UltraSim simulator that analog signals ana_en* and X1.Enanble have a logic low voltage of 0.5.
The vref statement sets the reference node of the input vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
If vref is not specified, the default value is 0 (that is, the ground). If this statement is specified more than once, the last value is used for the active mask.
tells the Virtuoso UltraSim simulator to set the negative node of the vector source to ground.
tells the simulator to set the negative node of the vector source to vss.
The vth statement sets the threshold voltage of the output vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all output vectors.
If vth is not specified, the default value is 1.65. If this statement is specified more than once, the last value is used for the active mask.
The hlz statement specifies the output resistance for the corresponding input vector, but unlike outz, this output resistance only applies to the H and L states of the vector. This resistance overwrites the resistance for the H and L states set by outz.
If hlz is not specified, the default value follows outz. If hlz is set to 0, the Virtuoso UltraSim simulator uses 0.01 instead. If this statement is specified more than once, the last value is used for the active mask.
The outz statement specifies the output resistance for the corresponding input vector. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
If outz is not specified, the default value is 0.01. If outz is set to 0, the default value is used. If this statement is specified more than once, the last value is used for the active mask.
The triz statement specifies the output impedance when the corresponding input vectors are in tri-state. You can provide a mask to specify which vector and bit to apply. If the mask is not specified, the setting applies to all input vectors.
If triz is not specified, the default value is 1,000 Meg. If triz is set to 0, the Virtuoso UltraSim simulator uses 0.01 instead. Also, if this statement is specified more than once, the last value is used for the active mask.
This section describes the values of signals at specified times (absolute or period time modes). For periodic signals, it is unnecessary to specify the absolute time at each time point. The period statement can be used to specify the signal period.
Time1 vector1_value1 vector2_value1 vector3_value1
Time2 vector1_value2 vector2_value2 vector3_value2
TimeN vector1_valueN vector2_valueN vector3_valueN
vector1_value1 vector2_value1 vector3_value1
vector1_value2 vector2_value2 vector3_value2
vector1_valueN vector2_valueN vector3_valueN
vector_value can be 0-9, A-F, Z, X, L, H, or U, and is dependent on how radix is set.
Tabular data is used to describe the waveform of voltage sources.
Note: This example assumes the period has been set by period 10.0.
The valid values in tabular data depend on the radix statement setting.
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Value Specified in |
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The values specified in the table above are converted into 0 and 1 states by the Virtuoso UltraSim simulator. The simulator also accepts L, H, Z, X, and U values when radix=1.
The Virtuoso UltraSim simulator accepts the following signal states for input vector signals.
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Z, z |
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X, x |
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L, l |
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H, h |
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U, u |
The resistance values of L and H are set by the hlz statement, and the impedance value of Z is set by the triz statement.
The Virtuoso UltraSim simulator accepts the following signal states for output vector signals.
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Z, z |
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X, x |
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U, u |
The Virtuoso UltraSim simulator converts the digital vector waveform into a PWL waveform. The rising/falling edge occurs at the switching state point of the digital waveform, as shown in Figure 11-3.
Figure 11-3 Conversion of Digital Waveform to PWL Waveform
The waveform format is defined by the wf_format option in the analog netlist file. A maximum of two waveform files are generated for one or more digital vector files. The expected waveform filename is netlist.vecexp.trn (PSF, FSDB, etc.) and the output vector is signal_name_exp. The comparison waveform filename is netlist.vecerr.trn (PSF, FSDB, etc.) and each comparison waveform is signal_name_err.
The comparison result values include,
0 - matched
1 - mismatched
X - ignored (output vector = X or bi-directional vector at input stage are possible causes)
In addition to the individual comparison result waveforms, the simulator generates a single vec_error waveform to indicate the overall comparison results. Waveform vec_error equals 1 when any of the individual comparison result waveforms also have a value of 1 (X is treated as 0).
; enable generation of expected output vectors and comparison result waveforms.
; radix specifies the number of bit of the vector.
; io defines the vector as an input or output vector.
; vname assigns the name to the vector.
; trise specifies the rise time of each input vector.
; tfall specifies the fall time of each input vector.
; vih specifies the logic high voltage of each input vector.
; vil specifies the logic low voltage of each input vector
; voh specifies the logic high voltage of each output vector
; vol specifies the logic low voltage of each output vector
Bidirectional signals can be divided into two columns, one for an input vector and the other for an output vector (the enable signal is no longer needed). The same vname and signal name is used for the input and output vectors.
For the input stage, the value of the output vector must be X or x (output vector check is not performed). For the output stage, the value of the input vectors must be Z or z (no stimulus for this signal). For example:
Use .probe tran v(*) depth=1 to probe the top-level signals and then check the waveform outputs with the Virtuoso Visualization and Analysis or SimVision viewers.
Note: The signal names are case sensitive.
A netlist.veclog file is generated at the location specified by the Virtuoso UltraSim simulator option-raw statement if there are any vector checks. A netlist.vecerr file is also generated when errors occur during the vector check. Refer to these two files for detailed information about the vector check.