2 

Netlist File Formats

The Virtuoso^® UltraSim^™ simulator recognizes SPICE, Spectre^®, Verilog^®-A, and structural Verilog netlist files. This chapter describes the syntax rules, elements, and command cards supported by the Virtuoso UltraSim simulator, and also describes the known limitations.

Supported Netlist File Formats

You can use the Virtuoso UltraSim simulator to simulate Spectre and HSPICE (registered trademark of Synopsys, Inc.) netlist files. Spectre and HSPICE netlist file formats follow different case sensitivity and naming convention rules. These differences affect interpretation of the netlist file devices, elements, parameters, topology, and simulator option statements. When setting up a Virtuoso UltraSim simulation, it is important to understand the differences in syntax rules, so the simulation produces the correct results.

The following netlist file formats are supported:

Note: Cadence recommends using either the Spectre or HSPICE languages exclusively in a netlist file.

Spectre

If the netlist file is in Spectre format, you need to set the -spectre command line option or add the .scs extension to your top-level netlist file. In this case, the Virtuoso UltraSim simulator behaves the same as Spectre, and applies Spectre naming conventions and case sensitivity to:

The Virtuoso UltraSim simulator also uses Spectre default values for model and simulation setup.

All of the Virtuoso UltraSim simulator options are available in Spectre syntax format, so you can define the options in a Spectre netlist file. The most common Virtuoso UltraSim simulator option is usim_opt. The Spectre syntax is located under the Spectre Syntax heading in each Virtuoso UltraSim option section.

Example

Spectre Syntax:

simulator lang=spectre

usim_opt sim_mode=ms speed=6 postl=2

usim_opt sim_mode=a inst=i1.i2.vco1

usim_pa chk1 subckt inst=[i1.i2] time_window=[1u 5u]

dcheck chk1 vmos model=[tt] inst=[i1.*] vgsu=1.0 vgsl=0.5 probe=1

usim_report resistor type=distr rmin=0 rmax=20

HSPICE

If you simulate a design that uses HSPICE format in the netlist file, you need to use Virtuoso UltraSim format without the -spectre command line option or .scs extension. In this case, the Virtuoso UltraSim simulator behaves the same as HSPICE, and applies HSPICE naming conventions and case insensitivity to:

The Virtuoso UltraSim simulator also uses HSPICE default values for model and simulation setup.

All of the Virtuoso UltraSim simulator options are available in SPICE syntax format, so you can define the options in a HSPICE netlist file. The most common Virtuoso UltraSim simulator option is .usim_opt. SPICE syntax is located under the SPICE Syntax heading of each Virtuoso UltraSim option section.

Example

HSPICE Syntax:

.usim_opt sim_mode=ms speed=6 postl=2

.usim_opt sim_mode=a inst=x1.x2.vco1

.usim_pa chk1 subckt inst=[x1.x2] time_window=[1u 5u]

.dcheck chk1 vmos model=[tt] inst=[x1.*] vgsu=1.0 vgsl=0.5 probe=1

.usim_report resistor type=distr rmin=0 rmax=20

Table 2-1 compares Virtuoso UltraSim simulator option syntax rules for HSPICE and Spectre netlist files.

 

Table 2-1  HSPICE and Spectre Syntax Comparison Table 

HSPICE Syntax	Spectre Syntax
HSPICE Language Rules: Case insensitive HSPICE compatible models Global parameter passing (parhier=global) temp=tnom and tnom=25 Built-in parameters: time, temp, hertz 0, gnd, gndl, and ground are all global ground nodes, and are reported as v(0) Command Line: ultrasim file (except file.scs)	Spectre Language Rules: Case sensitive Spectre compatible models Local parameter passing temp=27 and tnom=27 Built-in parameters: time, temp, tnom, scale, scalem, freq First node in global statement is ground node Command Line: ultrasim -spectre file or ultrasim file.scs
All files are required to be in HSPICE format.	All files with a .scs extension are assumed to be in Spectre format and all other files are assumed to be in HSPICE format. If files contain Spectre syntax, but do not use the .scs extension, they need to contain simulator lang=spectre at the beginning of the file to inform the Virtuoso UltraSim simulator that the content is in Spectre format.
HSPICE Netlist and Models: .model, .subckt, .ends, .end, ...	Spectre Netlist and Models: model, subckt, end, simulator lang=..., inline, ...
HSPICE Analysis and Options: .tran, .probe, .op, .meas, .ic, .data, .options, .temp, .alter, ...	Spectre Analysis and Options: tran, options, ic, save, altergroup
Verilog-A: .hdl Virtuoso UltraSim Structural Verilog: .vlog_include	Verilog-A: ahdl_include Virtuoso UltraSim Structural Verilog: vlog_include
Virtuoso UltraSim Vector Stimuli: .vec, .vcd, .evcd	Virtuoso UltraSim Vector Stimuli: vec_include, vcd_include, evcd_include
Virtuoso UltraSim Options and Analyses: .usim_opt, .usim_ta, .usim_nact, .pcheck, .dcheck, .acheck, .usim_save, .usim_restart, .usim_report, ...	Virtuoso UltraSim Options and Analyses: usim_opt, usim_ta, usim_nact, pcheck, dcheck, acheck, usim_save, usim_restart, usim_report, ...
The Virtuoso UltraSim simulator behaves like HSPICE (cannot be mixed with Spectre syntax).	The Virtuoso UltraSim simulator behaves like Spectre, and Spectre and SPICE syntax can be mixed using lang simulator=spice|spectre lookup=spice|spectre. Cadence recommends using a Spectre-only format netlist file.

Mixed Spectre and HSPICE

In some cases, a mix of the Spectre and HSPICE languages is required. For example, when a design uses Spectre format in the netlist file and the device models are only available in HSPICE format. Since HSPICE does not support using mixed languages in a netlist file, the Virtuoso UltraSim/Spectre -spectre command can be used to simulate the mixed format file.

Note: Use the simulator lang=spectre|spice command to switch between the Spectre and HSPICE languages in the netlist file.

Example

Spectre/HSPICE Mixed Syntax:

simulator lang=spectre

global 0 2

v1 (2 0) vsource dc=2.0

...

mos (4 2 0 0) nmos1

tran1 tran tstop=100n

...

simulator lang=spice lookup=spectre

.model nmos1 nmos level=49 version = 3.1 ...

...

simulator lang=spectre

In this example, the lang=spectre|spice command defines the language rules for the section of the netlist file that follows the statement until the next lang=spectre|spice command is issued or the end of the file is reached.

The lookup=spectre portion of the simulator=spice command specifies that all node, device, and instance names follow the Spectre naming convention. This is necessary for proper mapping between nodes, devices, and instances in the Spectre and HSPICE sections of the netlist file.

Wildcard Rules

The Virtuoso UltraSim simulator allows you to use wildcards (*) in the .probe, .lprobe, .ic, .nodeset, and save statements, as well as in all of the Virtuoso UltraSim scopes, options, and checking features.

The following rules apply to wildcards:

Examples

Structural Verilog

Spectre Syntax

vlog_include "file.v" supply0=gnd supply1=vdd insensitive=no|yes

SPICE Syntax

.vlog_include "file.v" supply0=gnd supply1=vdd insensitive=no|yes

Description

The Virtuoso UltraSim simulator supports structural Verilog netlist files for verification of digital circuits. This approach is typically used for standard cell designs, where the Verilog netlist file is generated by synthesis tools, and SPICE subcircuits are available for all standard cells.

The most common approach is to use a top level SPICE file which contains the analysis statement, probes, measures, and simulation control statements, and also calls one or multiple Verilog netlist files. The Verilog netlist files contain calls of the basic cells, which are available in the SPICE netlist file.

To activate the Verilog parser, use the Virtuoso UltraSim simulator -vlog option in the command line (for more information, refer to "Command Line Format" ). You can also include Verilog files by using the vlog_include statement(s).

The Virtuoso UltraSim simulator reads the structural Verilog file file.v. The keywords are supply0 and supply1. The supply0 keyword must be set to the ground node used in the Verilog subcircuit and supply1 must be set to the power supply node. If insensitive=yes, the Verilog netlist file is parsed case insensitive. If insensitive=no, it is parsed case sensitive. The default value is no.

Note: If the name of a module called by SPICE contains uppercase letters (for example, top_MODULE), then set insensitive=yes to use the vlog_include statement.

Unsupported Structural Verilog Features

The Virtuoso UltraSim simulator does not support the following structural Verilog features:

The Virtuoso UltraSim simulator resolves bus signals into individual signals when reading Verilog netlist files. The bus notation can be set using the buschar option and either <> or [].

The simulator also supports bus node mapping in structural Verilog. When instantiating the Verilog module in an analog netlist file, port mapping can only be based on the order of the signal name definitions. The bus node in the Verilog netlist file is expanded in the analog netlist file. When invoking an analog cell in a Verilog netlist file, port mapping can be based on the order of the signal definitions or names. For name mapping, the bus notation in the analog netlist file can be set using the vlog_buschar option.

Compressed Netlist File

The Virtuoso UltraSim simulator can read a compressed top-level netlist or included files (.include, .lib, .vec, .vcd, spf, and spef). The compressed netlist or included file needs to be compressed using gzip (.gz file extension).

Note: A compressed included file can be nested within another compressed file.

Example

ultrasim circuit.sp.gz

is a compressed circuit.sp file called circuit.sp.gz. A compressed model.gz file is nested within the circuit.sp file:

.include model.gz

Supported Spectre Model Features

Spectre

The Virtuoso UltraSim simulator recognizes circuit topologies in Spectre circuit simulator format for operating point and transient analysis. It does not support other analysis types, such as DC, AC, and noise.

For a detailed list and description of the related Spectre constructs, refer to the Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide.

The Virtuoso UltraSim simulator shares all device model interfaces with Spectre and therefore supports the same models:

Note: For more information about the sp32 model, refer to the "Surface Potential Based Compact MOSFET Model (spmos)" chapter in the Virtuoso Simulator Components and Device Models Reference.

The Virtuoso UltraSim simulator also supports the same set of customer models supported by Spectre, such as the Philips, ST, Infineon, and Nortel models.

Unsupported Spectre Features

The following Spectre components, analysis and controls, and features are not supported by the Virtuoso UltraSim simulator:

 

Components
assert	ucccs
core	uccvs
node	uvccs
paramtest	uvcvs
quantity	winding

 

Analysis and Controls
ac	pdisto	qpxf
alter	pnoise	set
check	psp	shell
dc	pss	sp
dcmatch	pxf	stb
envlp	qpac	sweep
montecarlo	qpnoise	tdr
noise	qpsp	xf
pac	qpss

 

Features
checkpoint	sens
export	spectremdl
param_limits	spectrerf

Virtuoso UltraSim device models are implemented using the Cadence compiled-model interface (CMI). You can also implement proprietary device models with CMI. For more information about installing and compiling device models using CMI, refer to Appendix C, "Using Compiled-Model Interface" in the Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide.

Verilog-A

Spectre Syntax

ahdl_include "file.va"

SPICE Syntax

.hdl "file.va"

Description

Verilog-A behavioral models can be applied to Spectre netlist files using the ahdl_include statement, and in HSPICE netlist files using .hdl.

Verilog-A behavioral language is used to model the behavior of analog design blocks. The Virtuoso UltraSim simulator supports Verilog-A behavioral language formats and provides a parser which is compatible with the Spectre simulator parser. Refer to the Cadence Verilog-A Language Reference for more information about supported language constructs.

Unsupported Verilog-A Features

The Virtuoso UltraSim simulator does not support the following Verilog-A features:

Note: The Fast SPICE technology used in the Virtuoso UltraSim simulator, such as representative device models, partitioning, and hierarchical simulation, cannot be applied to Verilog-A behavioral models (Verilog-A dominated designs will not show a performance advantage with the Virtuoso UltraSim simulator when compared to conventional SPICE tools).

Supported HSPICE Model Features

Syntax Rules

The Virtuoso UltraSim simulator syntax rules are similar to HSPICE syntax rules.

Note: You need to include a space after the colon (:) in the *relxpert: prefix.

The .t command does not work because .temp card also begins with .t.

Unit Prefix Symbols

The following unit prefix symbols can be applied to any numerical quantities:

Supported HSPICE Devices and Elements

The Virtuoso UltraSim simulator supports the following HSPICE devices and elements:

The following sections provide a brief description of the elements supported by the Virtuoso UltraSim simulator.

Bipolar Junction Transistor

Qxxx nc nb ne [ns] model_name [area = area_val] [areab = areab_val]

+ [areac = areac_val] [m = mval] [dtemp = dtemp_val]

Description

The Virtuoso UltraSim simulator ignores the initial condition parameters specified for bipolar junction transistors (BJTs). The BJTs supported by the simulator are listed below.

 

BJT level 1	Gummel-Poon model
BJT level 2	BJT Quasi-Saturation model
BJT level 6	Mextram model
BJT level 8	HiCUM model
BJT level 9	VBIC99 model

Arguments

 

nc, nb, ne	Collector, base, and emitter terminal node names.
ns	Substrate terminal node name; can also be set in a BJT model with the bulk or nsub parameters.
model_name	BJT model name.
area = area_val	Emitter area multiplying factor (default = 1.0).
areab = areab_val	Base area multiplying factor (default = area).
areac = areac_val	Collector area multiplying factor (default = area).
m = mval	Multiplier to indicate how many elements are in parallel. The m multiplier is used in a netlist file instance call (default value is m=1) The m parameter is set in the .subckt or .param statements Note: The multiplier is different from the m parameter. For example .subckt R_only up down m=5 R00 up down 100 m='m+2' .ends where m=5 in the .subckt statement is the m parameter definition and 'm+2' is an expression that is dependent on the m parameter in the subcircuit. The m located to the left of the equal (=) sign is a multiplier that is evaluated at 7 (5+2) to indicate seven resistors with a value of 100 ohms are in parallel. Notes The m parameter must be preset before use. The m multiplier does not need to be preset because it has a default value of 1. If m=5 is not defined in the example above, the simulation fails and produces an "undefined parameter" error message.
dtemp = dtemp_val	The difference between the element temperature and the circuit temperature in Celsius (default = 0.0).

Examples

In the following example

q001 c b a npn

defines a npn BJT q001 with its collector, base, and emitter connected to nodes c, b, and a, respectively.

In the next example

q002 5 8 19 6 pnp area = 1.5

defines a pnp BJT q002 with its collector, base, emitter, and substrate connected to nodes 5, 8, 19, and 6, respectively, and has an emitter factor of 1.5.

Capacitor

Cxx n1 n2 [model_name] [c = capacitance] [tc1 = val] [tc2 = val]

+ [scale = val] [m = mval] [w = val] [l = val] [dtemp = val]

or

Cxx n1 n2 poly c0 c1 ... [options shown above]

Description

If the instance parameter tags (such as c, tc1, and tc2) are not used, the arguments must be arranged in the same order as shown in the first syntax statement (see above). Otherwise, the instance arguments can appear in any order. In the second syntax statement, capacitance is determined by a polynomial function to be c = c0 + c1 * v + c2 * v *v + ..., where v is the voltage across the capacitor.

Arguments

 

n1, n2	Terminals of the capacitor.
model_name	Model name of the capacitor.
c = capacitance	Capacitance at room temperature. It can be a numerical value (in farads) or An expression with parameters and functions of node voltages Branch currents of other elements Time, frequency, or temperature The argument is optional if a model name is specified.
m = mval	Element multiplier used to simulate multiple parallel capacitors (default = 1).
tc1 = val	First-order temperature coefficient for the capacitor.
tc2 = val	Second-order temperature coefficient for the capacitor.
scale = val	Scaling factor; scales capacitance by its value (default = 1.0)
dtemp = val	Temperature difference between the element and the circuit in Celsius (default = 0.0)
l = val	Capacitor length in meters (default = 0.0)
w = val	Capacitor width in meters (default = 0.0)
c0, c1, ...	Coefficients of the polynomial form for the capacitance (if none exists, zero is used)

Examples

In the following example

c001 1 0 5f

defines a capacitor connected to nodes 1 and 0, with a capacitance of 5e-15 farad.

In the next example

c002 1 0 `1.5e-12*v(5)*time' tc1 = 0.001 tc2 = 0

defines a capacitor connected to nodes 1 and 0, with a capacitance depending on the voltage of node 5 and time.

In the next example

c003 1 0 poly 1 0.5 scale = 1e-12

defines a capacitor connected to node 1 and 0 with a capacitance determined by

c = [1 + 0.5 v (1,0) ] * le-12

In the next example

c004 1 0 c=10p M=5

defines five capacitors in parallel, measuring 10 picofarads, and connected to nodes 1 and 0.

Current-Controlled Current Source (F-Element)

Linear

Fxx n+ n- [cccs] vn1 gain [max = val] [min = val]

+ [scale = val] [tc1 = val] [tc2 = val] [abs = 1] [ic = val] [m=val]

Piece-Wise Linear

Fxx n+ n- [cccs] pwl(1) vn1 [delta = val] [scale = val]

+ [tc1 = val] [tc2 = val] [m = val] x1,y1 x2,y2 ... [ic = val] [m=val]

Polynomial

Fxx n+ n- [cccs] poly(ndim) vn1 [... vnndim]

+ [tc1 = val] [tc2 = val] [scale = val] [max = val]

+ [min = val] [m = val] [abs = 1] p0 [p1 ...] [ic = val] [m=val]

Delay Element

Fxx n+ n- [cccs] delay vn1 td = val [m=val]

+ [tc1 = val] [tc2 = val] [scale = val] [npdelay = val]

Description

Defines four forms of current-controlled current sources (CCCSs): Linear, piece-wise linear, polynomial, and delay element.

Arguments

 

n+, n-	Positive and negative terminals of the controlled source
cccs	Keyword for current-controlled current source (cccs is reserved for HSPICE and cannot be used as a node name)
gain	Current gain
poly	Keyword for polynomial dimension function (default is a one-dimensional polynomial) Note: Ndim must be a positive number.
pwl	Keyword for a piece-wise linear function
max = val	Maximum output current (default = undefined; no maximum set)
min = val	Minimum output current (default = undefined; no minimum set)
m = mval	Element multiplier to simulate multiple replication elements in parallel (default = 1)
tc1 = val	First order temperature coefficient for cccs
tc2 = val	Second order temperature coefficient for cccs
scale = val	Scaling factor which scales capacitance by its value (default = 1.0)
ic = val	Estimate of IC initial condition for the controlling currents, measured in amps (default = 0.0).
abs = 1	Output is an absolute value, if abs = 1
vn1	Names of voltage sources through which the controlling current flows
x1,...	Controlling current through the vn1 source (specify x values in increasing order)
y1,...	Corresponding output current values of x.
delay	Keyword for the delay element Note: delay is a reserved word that cannot be used as a node name.
td = val	Specifies the propagation delay for the macro model (subcircuit) process

Examples

In the following example

F001 1 0 VC 5 max=+3 min=-3

defines a cccs F001, connected to nodes 1 and 0 with a current value of I(F001)=5*I(VC). The current gain is 5, maximum current is limited to 3 amps, and minimum current is limited to -3 amps.

In the next example

F002 1 0 poly VC 1M 1.3M

defines a polynomial cccs F002, connected to nodes 1 and 0, and with a current value of I(F002)=1e-3+1.3e-3*I(VC).

In the next example

F003 1 0 delay VC td=7n scale=2

defines a delayed cccs F003, connected to nodes 1 and 0.

Current-Controlled Voltage Source (H-Element)

Linear

Hxx n+ n- [ccvs] vn1 transresistance [max = val] [min = val]

+ [scale = val] [tc1 = val] [tc2 = val] [abs = 1] [ic = val]

Piece-Wise Linear

Hxx n+ n- [ccvs] pwl(1) vn1 [delta = val] [scale = val]

+ [tc1 = val] [tc2 = val] x1, y1, x2, y2 ... [ic = val]

Polynomial

Hxx n+ n- [ccvs] poly(ndim) vn1 [... vnndim]

+ [tc1 = val] [tc2 = val] [scale = val] [max = val]

+ [min = val] [abs = 1] p0 [p1 ...] [ic = vals]

Delay Element

Hxx n+ n- [ccvs] delay vn1 td = val

+ [tc1 = val] [tc2 = val] [scale = val] [npdelay = val]

Description

Defines four forms of current-controlled voltage sources (CCVSs): Linear, piece-wise linear, polynomial, and delay element.

Arguments

 

n+, n-	Positive and negative terminals of the controlled source
ccvs	Keyword for current-controlled voltage source (ccvs is reserved for HSPICE and cannot be used as a node name)
transresistance	Current to voltage conversion factor
poly	Keyword for polynomial dimension function (default is a one-dimensional polynomial) Note: Ndim must be a positive number.
pwl	Keyword for a piece-wise linear function
max = val	Maximum output voltage (default = undefined; no maximum set)
min = val	Minimum output voltage (default = undefined; no minimum set)
m = mval	Element multiplier to simulate multiple replication elements in parallel (default = 1)
tc1 = val	First order temperature coefficient for ccvs
tc2 = val	Second order temperature coefficient for ccvs
scale = val	Scaling factor which scales capacitance by its value (default = 1.0)
ic = val	Estimate of IC initial condition for the controlling currents, measured in amps (default = 0.0).
abs = 1	Output is an absolute value, if abs = 1
vn1	Names of voltage sources through which the controlling current flows
x1,...	Controlling current through the vn1 source (specify x values in increasing order)
y1,...	Corresponding output current values of x.
delay	Keyword for the delay element Note: delay is a reserved word that cannot be used as a node name.
td = val	Specifies the propagation delay for the macro model (subcircuit) process

Example

In the following example

H001 1 0 VC 10 max=+10 min=-10

defines a ccvs H001, connected to nodes 1 and 0, with a voltage value of V(H001)=10*I(VC). The current to voltage gain is 5, maximum voltage is limited to 10 volts, and minimum voltage is limited to -10 volts.

Diode

Level = 1

Dxxx n+ n- model_name [area = area_val] [pj = pj_val] [wp = wp_val]

+ [lp = lp_val] [wm = wm_val] [lm = lm_val] [m = mval]

+ [dtemp = dtemp_val]

Level = 2

Dxxx n+ n- model_name [w = wval] [l = lval] [wp = wp_val] [lp = lp_val]

+ [ic = val] [m = mval]

Level = 3

Dxxx n+ n- model_name [w = wval] [l = lval] [wp = wp_val] [lp = lp_val]

+ [wm = wm_val] [lm = lm_val] [m = mval] [dtemp = dtemp_val]

Description

Defines a diode with terminal connections, model, and geometries. The [area,pj] or [w,l] format can be used to specify the diode area. Other instance parameters have the same meaning for both formats. Initial conditions are ignored for diode elements. Diode model levels 1-3 are supported by the Virtuoso UltraSim simulator. The diode capacitance is modeled as an equivalent linear capacitor between the terminals.

The diodes supported by the simulator are listed below.

 

Level 1	Geometric, junction diode model
Level 2	Fowler-Nordheim model
Level 3	Non-geometric, junction diode model
Level 4	Philips juncap model

Arguments

 

n+, n-	Positive and negative terminals of a diode, respectively.
model_name	Model name for the diode.
area = area_val	Area of diode without units for level=1 and m2 for level=3 (default = 1.0). Default value can be overridden from diode model. If unspecified, it is calculated from the width and length specifications: area = l*w.
pj = pj_val	Periphery of junction without units for level=1 and in meters for level=3 (default = 0.0). Default value can be overridden from diode model. If unspecified, it is calculated from the width and length specifications: pj = 2*(l+w).
w = wval	Width of junction in meters (default = 0.0).
l = lval	Length of junction in meters (default = 0.0).
wp = wp_val	Width of polysilicon capacitor in meters (default = 0.0).
lp = lp_val	Length of polysilicon capacitor in meters (default = 0.0).
wm = wm_val	Width of metal capacitor in meters (default = 0.0).
lm = lm_val	Length of metal capacitor in meters (default = 0.0).
dtemp = dtemp_val	The difference between the element temperature and the circuit temperature in Celsius (default = 0.0)
m = mval	Element multiplier (default = 1).

Examples

In the following example

d001 p n diode1

defines a diode named d001 connected between nodes p and n. The diode model is diode1.

In the next example

d002 5 10 diode2 area = 1.5

defines a diode named d002 connected between nodes 5 and 10. The diode model is diode2 and the PN junction area is 1.5.

Independent Sources

Voltage Source

Vxxx n+ n- [dc_func] [tran_func]

Current Source

Ixxx n+ n- [dc_func] [tran_func]

Description

Defines a voltage or current source. The direct current (DC) or one form of the transient functions is required, and only one form of the transient functions is allowed for each source. If a DC and a transient function coexist, the DC function is ignored even in a DC analysis. See "Supported HSPICE Sources" for a description of these source functions.

Arguments

 

n+, n-	Positive and negative terminals respectively
dc_func	DC function specifying a voltage or a current
tran_func	A form of transient function (see "Supported HSPICE Sources" for details)
m = m_val	Element multiplier (default = 1)

Examples

In the following example

v001 5 0 4.5

defines a voltage source between nodes 5 and 0 with a constant voltage of 4.5.

In the next example

v002 in gnd pulse( 0 4.5 100n 2n 2.5n 20n 25n )

defines a pulse voltage source between nodes in and gnd.

In the next example

i001 4 0 0.001

defines a current source between nodes 4 and 0 with a constant current 0.001A.

JFET and MESFET

Jxxx ndrain ngate nsource [nbulk] model_name [area=area] [w=width]

+ [l=length] [off] [ic=vdsval, vgsval] [m=val] [dtemp=val]

or

Jxxx ndrain ngate nsource [nbulk] model_name [area=area] [w=width]

+ [l=length] [off] [vds=vdsval] [vgs=vgsval] [m=val] [dtemp=val]

Description

Defines a JFET or metal semiconductor field effect transistor (MESFET) with terminal connections, models, and geometries. The required fields are the drain, gate, source nodes, and model name.

The JFET and MESFET models supported by the simulator are listed below.

 

Level 1	SPICE model
Level 2	Modified SPICE model
Level 3	SPICE compatible MESFET model

Arguments

 

Jxxx	JFET or MESFET element name. Note: Arguments must begin with J.
ndrain	Drain terminal node name.
ngate	Gate terminal node name.
nsource	Source terminal node name.
nbulk	Bulk terminal node name (optional).
model_name	Field effect transistor (FET) model name.
area	Area multiplying factor in units of square meters (default=1.0).
w	FET gate width in meters.
l	FET gate length in meters.
off	Sets initial condition to off for this element in DC analysis (default=on).
ic=vdsval, vgsval	Initial internal drain source voltage (vds) and gate source voltage (vgs).
m	Multiplier used to simulate multiple JFETs and MESFETs in parallel. Setting m affects all currents, capacitances, and resistances (default=1.0).
dtemp	The difference between the element temperature and the circuit temperature in Celsius (default=0.0)

Examples

In the following example

J001 ndrain ngate nsource jfet

defines a JFET with the name J001 that has its drain, gate, and source connected to nodes ndrain, ngate, and nsource, respectively.

In the next example

J002 nd ng ns jfet area=100u

Defines a JFET with the name J002 that has its drain, gate, and source connected to nodes nd, ng, and ns, and the area is 100 microns.

Lossless Transmission Line (T-Element)

Txx in ref_in out ref_out z0 = z0val td = tdval [l = length]

Description

Defines the lossless transmission line.

Arguments

 

in, out	Input and output node names
ref_in, ref_out	Ground reference node names for input and output signals
z0 = z0val	Characteristic impedance in ohms
td = tdval	Transmission delay time in second/meter
l = length	Transmission line length in meters (default = 1)

Example

T1 1 r1 2 r2 z0 = 100 td = 1n l = 1

Defines a lossless transmission line connected to nodes 1 and 2, and reference nodes r1 and r2. The transmission line is one meter long, with an impedance of 100 ohms and a delay of 1 ns per meter.

Lossy Transmission Line (W-Element)

Wxx in1 in2 … inN ref_in out1 out2 … outN ref_out <rlgcmodel=name | rlgcfile=name>

n=val l=val

Description

Defines the multi-conductor lossy frequency-dependent transmission line or W-element.

Arguments

 

in1 … inN	Node names for the near-end input signal terminals
ref_in	Node name for the near-end reference terminal
out1 … outN	Node names for the far-end signal terminals
ref_out	Ground reference node name for the far-end output terminal
n	Number of signal conductors, excluding the reference conductor
l	Length of the transmission line in meters
rlgcmodel	Name of the resistance, inductance, conductance, and capacitance (RLGC) model
rlgcfile	Name of the external file with RLGC parameters

Examples

In the following example

w1 1 r1 2 r2 rlgcmodel=t1_model n=1 l=0.5

.model t1_model w modeltype=rlgc n=1

+ Lo = 3e-7 Co = 1e-10 Ro = 10 Go = 0 Rs = 1e-03 Gd = 1e-13

w1 is a lossy transmission line connected to nodes 1 and 2, and reference nodes r1 and r2. It has a length of 0.5 m and its electrical characteristic is specified by the RLGC model t1_model.

In the next example

w2 1 2 3 r1 4 5 6 r2 rlgcmodel=t3_model n=3 l=0.2

.model t3_model w modeltype=rlgc n=3

+ Lo =

+ 1e-6

+ 2e-7 3e-6

+ 4e-8 5e-7 6e-6

+ Co =

+ 1e-11

+ -2e-12 3e-11

+ -4e-13 -5e-12 6e-11

+ Ro =

+ 40

+ 0 40

+ 0 0 40

+  Go =

+ 1e-4

+ -2e-5 3e-4

+ -4e-6 -5e-5 6e-4

+ Rs =

+ 1e-3

+ 0 1e-3

+ 0 0 1e-3

+ Gd =

+ 1e-13

+ -2e-14 3e-13

+ -4e-15 -5e-14 6e-13

w2 is a three-conductor lossy transmission line with a length of 0.2 m. Its electrical characteristic is specified by the RLGC matrix model t3_model.

In the next example

w3 1 2 3 r1 4 5 6 r2 rlgcfile = tline.dat n=3 l=0.1

w3 is a lossy transmission line connected to nodes 1, 2 and 3, and reference nodes r1 and r2. It has a length of 0.1 m and its electrical characteristic is specified by the RLGC model tline.dat file.

Format of the model file tline.dat:

* The first number specifies the number of conductors.

3

* Lo =

1e-6

2e-7 3e-6

4e-8 5e-7 6e-6

* Co =

1e-11

-2e-12 3e-11

-4e-13 -5e-12 6e-11

* Ro =

40

0 40

0 0 40

* Go =

1e-4

-2e-5 3e-4

-4e-6 -5e-5 6e-4

* Rs =

1e-3

0 1e-3

0 0 1e-3

* Gd =

1e-13

-2e-14 3e-13

-4e-15 -5e-14 6e-13

specifies the electrical characteristics of the w3 lossy transmission line by the external model file tline.dat.

MOSFET

Mxx ndrain ngate nsource [nbody] model_name [l = length] [w = width]

+ [ad = ad_val] [as = as_val] [pd = pd_val] [ps = ps_val]

+ [nrd = nrd_val] [nrs = nrs_val] [rdc = rdc_val] [rsc = rsc_val]

+ [m = mval] [dtemp = dtemp_val] [geo = geo_val]

or

Mxx ndrain ngate nsource [nbody] model_name [length] [width] [ad] [as] [pd] [ps]

Description

Defines a metal oxide semiconductor (MOS) transistor with terminal connections, model, and geometries. Besides the element name, only the model name and the drain, gate, and source nodes are required. Initial conditions can be specified, but are ignored by the Virtuoso UltraSim simulator.

The second syntax is used in conjunction with .options wl, which changes the order so that width appears before length. The second syntax requires the instance parameters to be listed in the order given above. If more than six instance parameters are listed, an error is issued by the Virtuoso UltraSim simulator.

The MOSFET models supported by the simulator are listed below.

 

Level 49 and Level 53	BSIM3v3 versions 3.0, 3.1, 3.2, 3.21, 3.22, 3.23, 3.24, and 3.30
Level 54	BSIM4 versions 4.0, 4.1, 4.2, 4.3, 4.4, and 4.5
Level 69	PSP model
Level 57 and Level 59	BSIM3SOI versions 2.2, 2.21, 2.22, 2.23, 3.0, 3.1, and 3.2 (Level 59 is a SOI FD model and the Virtuoso UltraSim simulator only supports this model in s mode)
Level 70	BSIMSOI 4.0
Level 61	RPI a-Si TFT model
Level 62	RPI Poli-Si TFT model versions 1 and 2
HVMOS (Level 101)	Cadence proprietary high-voltage MOS model
Level 50	Philips MOS9 model
Level 63	Philips MOS11 model
EKV (Level 55)	-

Arguments

 

ndrain, ngate, nsource	Drain, gate, and source terminals of the MOS transistor, respectively.
nbody	Bulk terminal node name; set in a MOS model with parameter bulk.
model_name	Name of the model for the transistor.
l = length	Channel length of the transistor in meters.
w = width	Channel width of the transistor in meters.
ad = ad_val	Drain diffusion area.
as = as_val	Source diffusion area.
pd = pd_val	Drain diffusion perimeter.
ps = ps_val	Source diffusion perimeter.
nrd = nrd_val	Number of squares for drain diffusion.
nrs = nrs_val	Number of squares for source diffusion.
rdc = rdc_val	Additional drain resistance, units of ohms. This value overrides the rdc setting in the MOS model specification (default = 0.0).
rsc = rsc_val	Additional source resistance, units of ohms. This value overrides the RSC setting in the MOS model specification (default = 0.0).
m = mval	Multiplier to simulate multiple MOSFETs in parallel (default=1).
dtemp = dtemp_val	The difference between the element temperature and the circuit temperature in Celsius (default = 0.0).
geo = geo_val	Source/drain sharing selector for MOS model parameter value acm = 3 (default = 0.0).

Examples

In the following example

m001 1 2 3 nmos

defines a MOS transistor with name m001 and model name nmos. The drain, gate, and source are connected to nodes 1, 2, and 3, respectively. The bulk terminal is defined in the N-channel metal oxide semiconductor (NMOS) model, or the default value 0 is used. l and w are chosen as default values in this case.

In the next example

m002 a b c d nmos l = 0.2u w = 1u

defines a MOS transistor with the name m002 and model name nmos. The drain, gate, source, and bulk are connected to nodes a, b, c, and d, respectively. l is 0.2 microns and w is 1 micron.

Mutual Inductor

Kxx Lyy Lzz [k = coupling]

Description

Defines a mutual inductor, where Lyy and Lzz are inductors. Other HSPICE mutual inductor formats are not supported.

Arguments

 

Lyy, Lzz	Mutually coupled inductors.
k = coupling	Coefficient of mutual coupling. k is a unitless number with a magnitude greater than 0 and less than or equal to 1. If k is negative, the direction of coupling is reversed.

Example

K1 L1 L2 0.1

Defines a mutual inductor with a coefficient of 0.1 between inductor L1 and inductor L2.

Resistor

Rxx n1 n2 [model_name] [[r =] val] [tc1 = val] [tc2 = val]

+ [scale = val] [m = val] [dtemp = val] [l = val] [w = val]

+ [c = val]

Description

Defines a linear resistor or wire element. If a resistor model is specified, the resistance value is optional. If the instance parameter tags (r, tc1, and tc2) are not used, the values must be ordered as shown above.

Arguments

 

n1, n2	Resistor terminal nodes.
model_name	Model name of the resistor.
r = val	Resistance value in ohms at room temperature. It can be a numerical value or An expression with parameters and functions of node voltages Branch currents of other elements Time, frequency, or temperature
m = mval	Multiplier to simulate multiple resistors in parallel (default = 1).
tc1 = val	First-order temperature coefficient for the resistor.
tc2 = val	Second-order temperature coefficient for the resistor.
scale = val	Scaling factor; scales resistance and capacitance by its value (default = 1.0).
dtemp = val	Temperature difference between the element and the circuit in Celsius (default = 0.0).
l = val	Resistor length in meters (default = 0.0).
w = val	Resistor width in meters (default = 0.0).
c = val	Parasitic capacitance connected from node n2 to the bulk node (default = 0.0).

Examples

In the following example

r001 1 0 50

defines a resistor named r001 with 50 ohms resistance connected between nodes 1 and 0.

In the next example

r002 x y 150 tc1 = 0.001 tc2 = 0

defines a 150 ohm resistor r002 between nodes x and y with temperature coefficient tc1 and tc2.

In the next example

r003 1 2 `5*v(5, 6)^2+f(x,y)'

defines a resistor connected to nodes 1 and 2, with a resistance depending on voltage deference between nodes 5 and 6 in the given expression.

Self Inductor

Lxx n1 n2 [l = lval] [model_name] [tcl = val] [tc2 = val]

+ [scale = val] [ic = val] [m = mval] [r = val] [dtemp = val]

Description

Defines a linear inductor, where n1 and n2 are the terminals. Other HSPICE self inductor formats and instance parameters are not supported.

Arguments

 

n1, n2	Inductor terminal nodes
l = lval	Inductance of the inductor (in Henries)
m = mval	Multiplier to simulate parallel inductors (default = 1)
tc1 = val	First-order temperature coefficient for the inductor
tc2 = val	Second-order temperature coefficient for the inductor
scale = val	Scaling factors; scales inductance by its value (default = 1.0)
ic = val	Initial current through an inductor (this value is used as the DC operating point current when uic is specified in the .tran statement, and can be overwritten with an .ic statement)
dtemp = val	Temperature difference between the element and the circuit in Celsius (default = 0.0)
r = val	Resistance of the inductor in ohms (default = 0.0)

Examples

In the following example

L001 1 0 5e-6

defines an inductor named L001 with an inductance of 5e-6 Henry connected between nodes 1 and 0.

In the next example

L002 x y 1.5e-6 tc1 = 0.001 tc2 = 0

defines an inductor named L002 with an inductance of 1.5e-6 Henry between nodes x and y. The temperature coefficients are 0.001 and 0.

In SPICE format:

l1 1 2 1n ic=1.0u

In Spectre format:

l1 1 2 inductor l=1n ic=1.0u

or

l1 1 2 inductor l=1n

ic l1:1=1.0u

Note: The Virtuoso UltraSim simulator provides hierarchical detection of inductor loops and generates an error message when an illegal inductor loop is detected. If you receive an inductor loop error message, remove the loop from the netlist file before running the circuit simulation again.

Voltage-Controlled Current Sources (G-Elements)

Voltage-Controlled Capacitor

Gxx n+ n- vccap pwl(1) in+ in- [delta = val] [scale = val]

+ [m = val] [tc1 = val] [tc2 = val] x1, y1, x2, y2 ... [ic = val]

Voltage-Controlled Current Source

Behavioral

Gxx n+ n- [vccs] cur = 'equation' [max = val] [min = val] [scale = val]

Linear

Gxx n+ n- [vccs] in+ in- transconductance [max = val] [min = val]

+ [m = val] [scale = val] [tc1 = val] [tc2 = val] [abs = 1] [ic = val]

Piece-Wise Linear

Gxx n+ n- [vccs] pwl(1) in+ in- [delta = val] [scale = val]

+ [m = val] [tc1 = val] [tc2 = val] x1, y1, x2, y2 ... [ic = val]

Polynomial

Gxx n+ n- [vccs] poly(ndim) in+ in- ... inndim+ inndim-

+ [tc1 = val] [tc2 = val] [scale = val] [max = val]

+ [min = val] [abs = 1] p0 [p1 ...] [ic = vals]

Delay Element

Gxx n+ n- [vccs] delay in+ in- td = val

+ [tc1 = val] [tc2 = val] [scale = val] [npdelay = val]

Voltage-Controlled Resistor

Linear

Gxx n+ n- vcr in+ in- transfactor [max = val] [min = val]

+ [m = val] [scale = val] [tc1 = val] [tc2 = val] [ic = val]

Piece-Wise Linear

Gxx n+ n- vcr pwl(1) in+ in- [delta = val] [scale = val]

+ [m = val] [tc1 = val] [tc2 = val] x1, y1, x2, y2 ... [ic = val]

Gxx n+ n- vcr npwl(1) in+ in- [delta = val] [scale = val]

+ [m = val] [tc1 = val] [tc2 = val] x1, y1, x2, y2 ... [ic = val]

Gxx n+ n- vcr ppwl(1) in+ in- [delta = val] [scale = val]

+ [m = val] [tc1 = val] [tc2 = val] x1, y1, x2, y2 ... [ic = val]

Polynomial

Gxx n+ n- vcr poly(ndim) in+ in- ... inndim+ inndim-

+ [tc1 = val] [tc2 = val] [scale = val] [max = val]

+ [min = val] [abs = 1] p0 [p1 ...] [ic = vals]

Description

Defines voltage-controlled current sources (VCCSs), voltage-controlled resistors (VCRs), and voltage-controlled capacitors (VCCAPs) in behavioral, linear, piece-wise linear, poly, and delay forms. In the behavioral function, the equation can contain terms of node voltages. In linear form, the output value is estimated with `[v(in+)-v(in-)]' multiplied by transfactor or transconductance, followed by the scale and temperature adjustment, before confined with the abs, min, and max parameters. In the piece-wise linear function, at least two pairs of voltage-current (or voltage-resistance, voltage-capacitance) points are required.

Arguments

 

n+, n-	Terminals of controlled element.
in+, in-	Positive and negative controlling nodes.
vcr, vccap, vccs	Keywords for the voltage-controlled resistor, capacitor, and current source elements. Note: vcr, vccap, and vccs are reserved words that cannot be used as node names.
cur = 'equation'	Current of the controlled element flowing from n+ to n-. It can be An expression with parameters and functions of node voltages Branch currents of other elements Time, frequency, or temperature
max = val	Maximum value of the controlled current or resistance.
min = val	Minimum value of the controlled current or resistance.
transconductance	Voltage to current conversion factor.
transfactor	Voltage to resistance conversion factor.
scale = val	Scaling factor; scales current by its value (default = 1.0).
m = val	Multiplier (default = 1).
tc1 = val	First-order temperature coefficient for the element.
tc2 = val	Second-order temperature coefficient for the element.
abs	Output current takes its absolute value if abs = 1.
ic = val	Initial value of the current source (default = 0.0).
delta = val	A value used to smooth corners of the piece-wise linear function. The default is 1/4 of the smallest distance between break points, and is not to exceed 1/2 of this value.
x1...	Voltage drops between the controlling nodes in+ and in-. They must be in ascending order.
y1...	Element output value corresponding to x1...
npdelay	The number of data points used in delay simulations.

The npwl and ppwl functions are used to interchange the n+ and n- nodes, but use the same transfer function.

npwl

For the in- node connected to n+, if v(n+,n-) < 0, then the controlling voltage is v(in+,in-). Otherwise, the controlling voltage is v(in+,n-).

For the in- node connected to n-, if v(n+,n-) > 0, then the controlling voltage is v(in+,in-). Otherwise, the controlling voltage is v(in+,n+).

ppwl

For the in- node, connected to n+, if v(n+,n-) > 0, then the controlling voltage is v(in+,in-). Otherwise, the controlling voltage is v(in+,n-).

For the in- node, connected to n-, if v(n+,n-) < 0, then the controlling voltage is v(in+,in-). Otherwise, the controlling voltage is v(in+,n+).

Note: If the in- node does not connect to either n+ or n-, the Virtuoso UltraSim simulator changes npwl and ppwl to pwl.

Examples

In the following example

G1 1 2 cur = '3.0*sin(v(7)/2)+v(6)^2'

defines a VCCS connected to nodes 1 and 2, with its current dependent on the voltage of nodes 6 and 7 in the given form.

In the next example

G2 1 2 vccs 5 0 0.5 max = 5 min = 0 m = 2 ic = 0

defines a VCCS connected to nodes 1 and 2. Its current is initialized as 0, and is half of the voltage at node 5. The current is also confined within 0 and 5 amps. The output current is multiplied by 2.

In the next example

G3 1 2 vccs pwl(1) 5 0 delta = 0.2 0, 0 0.5,1 1.5,1.5 scale = 1.e-3

defines a VCCS connected to nodes 1 and 2, its current controlled by the voltage at node 5. The current is calculated in a piece-wise linear function with a smoothing parameter of 0.2, and is scaled by 1.e-3 upon output.

In the next example

Gres 1 2 vcr pwl(1) 5 4 m = 3 0,0 1,1k 2,1.5k 3,1.8k 4,2.0k 5,2.0k ic = 1k

defines a VCR connected to nodes 1 and 2, with its resistance dependent on the voltage difference between nodes 5 and 4 in a piece-wise linear form. The initial resistance is 1k. The output resistance is decreased by 2/3.

In the next example

Gcap 1 2 vccap pwl(1) 5 4 m = 3 scale = 1.e-12 0,0 1,10 2,15 3,18 4,20 5,20 ic = 10

defines a VCCAP connected to nodes 1 and 2, with its capacitance dependent on the voltage difference between nodes 5 and 4 in a piece-wise linear form. The initial capacitance is set to 10 p after being scaled with 1e-12. The output capacitance is increased by a factor of 3.

In the next example

Gnmos d s vcr npwl(1) g s m =3 0,5g 1,5meg 2,5k 3,1k 5,50

tells the Virtuoso UltraSim simulator to model the source-drain resistor of the n-channel MOSFET which is used as a switch. Based on the npwl function, the resistor value (Gnmos) does not change when changing the position of the d and s nodes.

Voltage-Controlled Voltage Source (E-Elements)

Behavioral

Exx n+ n- [vcvs] vol = 'equation' [max = val] [min = val]

Linear

Exx n+ n- [vcvs] in+ in- gain [max = val]

+ [min = val] [scale = val]

+ [tc1 = val] [tc2 = val] [abs = 1] [ic = val]

Piece-Wise Linear

Exx n+ n- [vcvs] pwl(1) in+ in- [delta = val] [scale = val]

+ [tc1 = val] [tc2 = val] x1 y1 x2 y2 ... [ic = val]

Polynomial

Exx n+ n- [vcvs] poly(ndim) in+ in- ... inndim+ inndim-

+ [tc1 = val] [tc2 = val] [scale = val] [max = val]

+ [min = val] [abs = 1] p0 [p1 ...] [ic = vals]

Delay Element

Exx n+ n- [vcvs] delay in+ in- td = val

+ [tc1 = val] [tc2 = val] [scale = val] [npdelay = val]

Laplace

Exx n+ n- laplace in+ in- k0, k1, ..., kn/ d0, d1, ..., dm

+ [tc1 = val] [tc2 = val] [scale = val]

Description

Defines six forms of voltage-controlled voltage sources (VCVSs): Behavioral, linear, piece-wise linear, polynomial, delay element, and Laplace. In behavioral form, the equation can contain terms of node voltages. In linear form, the output value is estimated using `gain*[v(in+)-v(in-)]', followed by the multiplication of scale and temperature adjustment, before being confined by the abs, min, and max parameters. In the piece-wise linear function, at least two pairs of voltage points are required.

Arguments

 

n+, n-	Terminals of the controlled element.
in+, in-	Positive and negative controlling nodes.
vol = 'equation'	Voltage of the controlled element. The equation can be a function of parameters, node voltages, and branch currents of other elements.
max = val	Maximum value of the controlled voltage.
min = val	Minimum value of the controlled voltage.
gain	Voltage gain.
scale = val	Scaling factor; scales voltage by its value (default = 1.0).
tc1 = val	First-order temperature coefficient for the element.
tc2 = val	Second-order temperature coefficient for the element.
abs	Output voltage takes its absolute value if abs = 1.
ic = val	Initial value of the voltage source (default = 0.0).
delta = val	A value used to smooth the corners in the piece-wise linear function. It is defaulted to be 1/4 of the smallest distance between break points, not to exceed one-half of this value.
x1...	Voltage drops between the controlling nodes in+ and in-. They must be in ascending order.
y1...	Element voltages corresponding to x1...
ndim	Polynomial dimension (default = 1).
p0, p1, ...	Polynomial coefficients. If one coefficient is specified, it is assumed to be p1 (p0 = 0.0), representing a linear element. If more than one coefficient is specified, it represents a non-linear element.
td	Time delay keyword.
npdelay	Sets the number of data points to be used in delay simulations.
k0, k1, ..., d0, d1, ...	Laplace coefficients.

Examples

In the following example

E1 1 2 vol = '3.0*sin(v(7)/2)+v(6)^2'

defines a VCVS that is connected to nodes 1 and 2, with its voltage dependent on nodes 6 and 7 in the given expression.

In the next example

E2 1 2 vcvs 5 0 0.5 max = 5 min = 0 ic = 0

defines a VCVS that is connected to nodes 1 and 2. Its voltage is initialized to be 0, and is half of the voltage of node 5. The final voltage is confined within 0 and 5 volts.

In the next example

E3 1 2 vcvs pwl(1) 5 0 delta = 0.2 0, 0 0.5,1 1.5,1.5

defines a VCVS that is connected to nodes 1 and 2, with its voltage dependent on the voltage of node 5. The voltage is calculated in a piece-wise linear function with a smoothing parameter delta = 0.2.

In the next example

E4 out 0 laplace in 0 0.0,0.0,0.0,1.0 / 1.0,2.0,2.0,3.0

defines a VCVS where the voltage v(out,0) is controlled by the voltage v(in,0) using the Laplace function.

Supported HSPICE Sources

Listed below are descriptions of the HSPICE DC and transient source functions that are supported by the Virtuoso UltraSim simulator for independent current and voltage sources.

dc

dc=dc_voltage

or

dc=dc_current

Arguments

 

dc=dc_voltage	The value of the DC voltage source
dc=dc_current	The value of the DC current source

Example

V1 1 0 [dc=] 5

Declares a voltage source named V1 with a DC voltage of 5 volts.

exp

exp [(] v1 v2 [td1 [tau1 [td2 [tau2]]]] [)]

Arguments

 

v1	Initial value of voltage or current in volts or amps
v2	Pulsed value of voltage or current in volts or amps
td1	Rise delay time in seconds (default = 0.0)
td2	Fall delay time in seconds (default = td1+tstep)
tau1	Rise time constant in seconds (default = tstep)
tau2	Fall time constant in seconds (default = tstep)

Example

I1 1 0 exp(-0.05m 0.05m 5n 25n 10n 20n)

Defines a current source named i1 that connects to node 1 and ground with an exponential waveform, which has an initial current of -0.05 mA at t=0, and a final current of 0.05 mA. At t=5ns, the waveform rises exponentially from -0.05 mA to 0.05 mA with a time constant of 25 ns. At t=10 ns, it starts dropping to -0.05 mA again, with a time constant of 20 ns.

pwl

pwl [(] t1 v1 [t2 v2 … tn vn] [r = repeat_time] [td = delay ] [)]

or

pl [(] v1 t1 [v2 t2 … vn tn] [r = repeat_time] [td = delay ] [)]

Arguments

 

t1 v1 t2 v2 ...	Time and value pairs describing a piece-wise linear waveform. The value is amps or volts, depending on the type of source.
r = repeat_time	Repeats the waveform indefinitely starting from the repeat_time time point.
td = delay	The time in seconds to delay the start of the waveform.

Example

v001 1 0 pwl( 0 5 9n 5 10n 0 12n 0 13n 5 15n 5 r = 9n)

Defines a voltage source named v001 that connects to node 1 and ground with a PWL waveform from 0 n to 15 n, continually repeating from 9 n to 15 n.

pwlz

pwlz [(] t1 v1 [t2 v2 ...ti Z... tn vn] [r = repeat_time] [td = delay ] [)]

Description

This function resembles the PWL function, except that some voltage values can be replaced by a keyword z, which stands for the high-impedance state. In this state, the voltage source is disconnected from the time point (with keyword z) to the following time point (with non-z state).

Example

v002 1 0 pwlz ( 0 Z 9n 5v 10n 0 12n 0 13n Z 15n 5v )

Defines a voltage source that connects to node 1 and ground with a PWLZ waveform from 9 ns to 13 ns, and from 15 ns to the end of simulation.

pulse

pulse [(] v1 v2 [td [tr [tf [pw [per]]]]] [)]

Arguments

 

v1	The initial voltage in volts
v2	The second voltage (the waveform swings between v1 and v2)
td	The time from the beginning of the transient to the first onset of the ramp (default = 0)
tr	The rise time of the pulse (default = tstep)
tf	The fall time of the pulse (default =tstep)
pw	The pulse width (default = tstop)
per	The period of the pulse (default = tstop)

Example

v001 1 0 pulse (0 5 0 1n 1n 5n 10n)

Defines a voltage source named v001 that connects nodes 1 and 0. The pulse waveform swings between 0 and 5 volts. The waveform has no initial delay, and has the rise and fall times as 1 ns. The total pulse width is 5 ns with a 10 ns period.

sin

sin [(] vo va [freq [td [theta [phase] ] ] ] [)]

Arguments

 

vo	Voltage or current offset in volts or amps.
va	Voltage or current root mean square (RMS) amplitude in volts or amps.
freq	Source frequency in Hz (default = 1/tstop).
td	Time delay before beginning the sinusoidal variation in seconds (default = 0.0), response is 0 volts or amps until the delay value is reached, even with a non-zero DC voltage.
theta	Damping factor in units of 1/seconds (default = 0.0).
phase	Phase delay in units of degrees (default = 0.0).

Example

In the following example

i001 1 0 sin(0.01m 0.1m 1.0e8 5n 1.e7 90)

defines a current source named i001 that connects to node 1 and ground with a sin waveform, and has an amplitude value of 0.1 mA, an offset of 0.01 mA, a 100 MHz frequency, a time delay of 5 ns, a damping factor of 1.e7, and a phase delay of 90 degrees.

Notes

pattern

pat [(] high low tdelay trise tfall tsample

+ bstring1 [rb=val] [r=val]

+ [bstring2 [rb=val] [r=val]] ... [)]

or

pat [(] high low tdelay trise tfall tsample

+ [component1 ... componentn] [rb=val] [r=val] [)]

Description

The pattern function defines a bit string (b-string) or a series of b-strings and consists of four states, 1, 0, m, and z, which represent the high, low, middle voltage or current, and high impedance states, respectively.

Arguments

 

pat	Keyword for a pattern time-varying source.
high	High voltage or current value of the pattern source in volts or amps.
low	Low voltage or current value of pattern source in volts or amps.
tdelay	Delay time in seconds from the beginning of the transient to the first ramp occurrence.
trise	Duration of the ramp-up in seconds.
tfall	Duration of the ramp-down in seconds.
tsample	Time spent at each 0, 1, m, or z pattern value in seconds.
bstring1	Defines a bit string consisting of 1, 0, m, or z. The first alphabetic character must be b. 1 represents the high voltage or current value. 0 is the low voltage or current value. m represents the value which is equal to 0.5*(vhigh+vlow). z represents the high impedance state (only for voltage source). Note: The b-string cannot contain parameters.
component1 ... componentn	Defines a series of b-strings. Each component is a b-string. rb and r can be used for each b-string. Note: Brackets [] must be used.
rb=val	Keyword to specify the starting bit or component to repeat. The number is counted from left to right. The default is rb=1 (source repeats from the most left-hand bit or component). The value of rb must be an integer. If the value is larger than the length of the b-string, or the total the number of components, an error is reported by the Virtuoso UltraSim simulator. If the value is less than 1, the simulator automatically sets it to the default value of 1. Note: The value of rb cannot be a parameter.
r=val	Keyword to specify how many times to repeat the b-string or the components. The default value is r=0 (no repeat). The value of r must be an integer. If r=-1, then the repeating operation runs continuously. If the value is less than -1, the simulator automatically sets it to the default value of 0. Note: The value of r cannot be a parameter.

Examples

In the following example

v1 1 0 pat (5 0 0n 1n 1n 5n b01000 r=1 rb=2 bm10z)

tells the Virtuoso UltraSim simulator to define an independent pattern voltage source named v1 with a first b-string 01000 that executes once and repeats once from the second bit 1, and then the second b-string m10z executes once (that is, the whole bit pattern is 010001000m10z). The high voltage 1 is 5 volts, low voltage 0 is 0 volts, middle voltage m is 2.5 volts, rise and fall times are both 1 ns, and each bit sample time is 5 ns.

In the next example

.param high = 1.5 low = 0 td=0 tr=10n tf=20n tsample=60n

V2 1 0 pat(high low td tr tf tsample

+ [b01000 r=1 rb=2 bm10z] RB=2 R=2)

tells the simulator to define an independent pattern voltage source named v2 with a whole bit pattern of 01000 1000 m10z m10z m10z.

Supported SPICE Format Simulation and Control Statements

Listed below are the Virtuoso UltraSim SPICE format simulation and control statements. The following sections provide a brief description of each statement.

.alter

.alter

Description

This statement is designed for repeating simulations under different conditions: Altered parameters, temperatures, models, circuit topology (different elements and subcircuit definitions), and analysis statements. Multiple .alter statements can be used in a netlist file, which is divided into several sections. The part before the first .alter statement is called the main block. Subsequent .alter statements and those between .alter and .end are referred to as alter blocks. When simulating an alter block, the information in the alter block is added to the main block, where conditions with identical names (for example, parameters, elements, subcircuits, and models) are replaced with those in the alter block. Analysis statements are treated in the same way.

The output from a sequence of altered simulations is distinguished by the number appended to the end of the filename, labeling the order in which they are generated. For example, the files from measures are named with .mt0, .mt1, and so forth. All the others skip the 0 for the first simulation, and appear as .fsdb, .trn, .dsn, .nact, .pa, .ta, .vecerr, and .veclog.

Examples

In the following example

V0 (net5 0) vsource type=pulse val0=0.0 val1=1 period=40n rise=10p \

fall=10p width=20n

C0 (cnode 0) capacitor c=cValue

R0 (net5 cnode) resistor r=1K

....

.alter

.param Cvalue=1pF

.alter

.param Cvalue=100pF

.alter

.param Cvalue=10fF

.end

the value of capacitor in the first simulation run is 1pf. In the second and third simulation runs, the values change to 100pf and 10fF respectively.

In the next example

.temp 25

.alter

.temp 50

the first simulation is run at 25 C and the second simulation is run at 50 C.

.connect

.connect node1 node2

Description

Use to connect node1 and node2.

Note: Both nodes must be at the same level of the design.

Arguments

 

node1, node2

Node names

Example

.connect vdd vdd!

Tells the simulator to connect the vdd and vdd! nodes. If probed, the nodes are retained in the waveform file.

.data

.data name param1 [param2 ...]

+ val11 [val21 ...]

+ val12 [val22 ...]

.enddata

Description

This statement allows you to perform data-driven analysis in which parameter values can be modified in different simulations. This statement is used in conjunction with an analysis statement (for example, .tran) with a keyword data = name.

The Virtuoso UltraSim simulator only supports an inline format for the .data statement.

Arguments

 

name	Specifies the data name used in analysis statements
param1, param2, ...	Specifies the parameter names used in the netlist file (the names must be declared in a .param statement)
val11, val21, ...	Specifies the parameter values

Example

.param res = 1 cap = 1f

.tran 1ns 1us sweep data = allpars

.data allpars res cap

+ 1k 1p

+ 10k 10p

.enddata

Tells the Virtuoso UltraSim simulator to perform two separate simulations with the two pairs of parameters: res and cap.

.end

.end

Description

This statement specifies the end of the netlist file description. All subsequent statements are ignored.

Example

*title

...

.end

.endl

.endl

Description

This statement specifies the end of a library definition.

Example

.lib tt

...

.endl tt

.ends or .eom

.ends

or

.eom

Description

These statements specify the end of a subcircuit definition. Subcircuit references or calls can be nested within subcircuits.

Examples

.subckt inv in out

...

.ends

or

.macro inv in out

...

.eom

.global

.global node1 [node2 ... noden]

Description

This statement defines global nodes. The Virtuoso UltraSim simulator connects all references to a global node name, which can be used at any hierarchical level, to the same node.

Example

.global vdd gnd

Tells the Virtuoso UltraSim simulator to define nodes vdd and gnd as global nodes.

.ic

.ic v(node1) = val1 [v(node2) = val2] ... [v(noden) = valn] subckt=subckt_name depth=depth_val

Description

This statement is used to specify an initial voltage condition for nodes. The Virtuoso UltraSim simulator forces the node voltage to the specified voltage at time=0. A node name can be hierarchical and can contain wildcards. The statement can be embedded in the scope of a subcircuit. In this case, the initial condition is assigned to the nodes local to the subcircuit. If a conflict occurs between an embedded IC and a hierarchical IC, the embedded one is adopted.

For more information about wildcards, see "Wildcard Rules".

Arguments

 

v(node)	Sets the initial voltage for the node. The node name can be hierarchical and can contain wildcards (for example, x?1.*.n*). In this case, the Virtuoso UltraSim simulator assigns the initial condition to all the nodes that match the name.
subckt	Specifies the subcircuit name (by default, applies to the top level). If the statement is already used in a subcircuit definition, this parameter is ignored. Setting the parameter is equivalent to defining the statement within a subcircuit declaration.
depth	Specifies the depth in the circuit hierarchy that a wildcard name applies to. This parameter is only available when the * wildcard is used in the output variable. If set to 1, only the nodes at the current level are applied (default value is infinity).

Example

.ic v(n1) = 0.5 v(n2) = 1.5 subckt=inv

Tells the Virtuoso UltraSim simulator to initialize node n1 to 0.5 V and node n2 to 1.5 V in all instances of subcircuit inv.

.include

.include [filepath]filename

Description

This statement inserts the contents of the file into the netlist file.

Note: [filepath]filename can be enclosed by single or double quotation marks.

Example

.include options.txt

Tells the Virtuoso UltraSim simulator to insert the options.txt file into the netlist file.

.lib

.lib [libpath] library_name section_name

Description

This statement is used to read common statements, such as device models, from a library file.

Arguments

 

[libpath]	Path to the library file
library_name	Name of the library file Note: The [libpath] library_name can be enclosed with single or double quotation marks.
section_name	Section of the library to be included

Example

.lib `models.lib' tt

Tells the Virtuoso UltraSim simulator to read the tt section from the models.lib library file.

.nodeset

.nodeset v(node1) = val1 [v(node2) = val2] ... [v(noden) = valn]

or

.nodeset node value

Description

This statement specifies the node set for the node. The Virtuoso UltraSim simulator forces the node voltage to the specified value at the first operating point iteration and then the solver calculates the node voltage used at time=0. A node name can be hierarchical and can contain wildcards. The statement can be embedded in the scope of a subcircuit. In this case, the initial condition is assigned to the nodes local to the subcircuit. If a conflict occurs between an embedded IC and a hierarchical IC, the embedded one is adopted.

For more information about wildcards, see "Wildcard Rules".

Note: The .nodeset statement can be used to enhance convergence in DC analysis. If the node value is set close to the actual DC operating point, convergence can be enhanced.

Arguments

 

v(node)

Sets the node set for the node. The node name can be hierarchical and contain wildcards (for example, x?1.*.n*). In this case, the Virtuoso UltraSim simulator assigns the initial condition to all the nodes that match the name.

Example

.nodeset v(n1) = 0.5 v(n2) = 1.5

The initial starting point for the operating point calculation is 0.5 V for n1 and 1.5 V for n2. The final operating point for both nodes may be slightly different since .nodeset is only used at the first iteration.

.op

.op [format] [time] [format] [time] [gzip=0|1]

Description

The .op command is used to perform an operating point analysis. The Virtuoso UltraSim simulator reports all node voltages in an .ic file. If multiple time points are specified, the Virtuoso UltraSim simulator saves the node voltages in the following order: The first time point in an .ic0 file and the second point in an .ic1 file.

In addition, the Virtuoso UltraSim simulator reports all the operating point information in a different file (the file name is dependent on the keyword format used). If time is not specified, the Virtuoso UltraSim simulator performs the operating point analysis at time 0. If transient analysis is not available, the Virtuoso UltraSim simulator performs the operating point analysis at time 0, even if a non-zero time is specified with the command.

The Virtuoso UltraSim simulator can print the operating point analysis in the following formats: ASCII, PSF ASCII, and PSF binary (default is ASCII). To specify PSF ASCII, use usim_opt wf_format=psfascii. To specify PSF binary, use usim_opt wf_format=psf.

Arguments

 

format	Specifies the report format and uses the following keywords: all, current, or voltage. Note: Only one argument keyword can be used at a time in a command (you only need to use the first letter of the keyword). Voltage tells the Virtuoso UltraSim simulator to print a voltage table for each node and information for each model. The information is saved in an ASCII voltage.op file. If PSF format is specified, the file name is tran_voltage_op.tran_op. All tells the Virtuoso UltraSim simulator to print a voltage table for all the nodes, information for each model, and operating point information for each element (voltage, current, conductance, power, and capacitance). The information is saved in an ASCII all.op file. If PSF format is specified, the file name is tran_all_op.tran_op. Refer to the Virtuoso UltraSim Waveform Interface Reference for more details on PSF files. Current tells the Virtuoso UltraSim simulator to print a voltage table, information for each model, and limited operating point information for each element (voltage, current, and power). The information is saved in an ASCII current.op file. If PSF format is specified, the file name is tran_current_op.tran_op.
time	Specifies the time at which the report is printed. This argument is placed directly after the all, current, and voltage arguments in the .op command.
gzip=0|1	Specifies whether the .op command should compress the output files. 0 (Default): Generates uncompressed files. 1: Generates gzip-compressed files.

Example

.op voltage .5ns current 1.0ns 2.0ns gzip=1

Tells the Virtuoso UltraSim simulator to calculate the operating point at 0.5 ns and print the .op information in voltage format. The operating points are also calculated at 1.0 ns and 2.0 ns and printed in current format. The simulator also generates a gzip-compressed output file.

Note: If you use .op [format] [time1] [time2], the format at time2 is the same as time1.

.options

.options argument1 [argument2] ...

Description

This statement defines a set of SPICE options. The Virtuoso UltraSim simulator recognizes dcap, defad, defas, defl, defnrd, defnrs, defpd, defps, defw, gmin, parhier, scale, scalm, search, and wl as arguments to this statement.

Arguments

 

co = 80|132	Defines the number of variables to be displayed on each line (default value is 80). If set to 80, generates a narrow printout containing up to four output variables per line. If set to 132, generates a wide printout containing up to eight output variables per line.
dcap	Equations calculate the depletion capacitance of the diodes (level=1|3) and BJTs.
defad	Default MOSFET drain diode area (ad). Default value is 0.
defas	Default MOSFET source diode area (as). Default value is 0.
defnrd	Default MOSFET drain resistor in number of squares (nrd). Default value is 0.
defnrs	Default MOSFET source resistor in number of squares (nrs). Default value is 0.
defpd	Default MOSFET drain diode perimeter (pd). Default value is 0.
defps	Default MOSFET source diode perimeter (pd). Default value is 0.
defw	Default MOSFET channel width. Default value is 1e-4.
gmin = value	The minimum conductance allowed for transient analysis. Default value is 1e-12.
lngold = 0|1|2	Defines the numerical printout formats for the .print statement. 0 - Engineering (default): 1.234K, 123M 1 - G (fixed and exponential): 1.234e+03, .123 2 - E (exponential SPICE): 1.234e+03, .123e-1 Note: Engineering format cannot be combined with exponential format.
parhier = (local|global)	Rules for parameter passing; applies only to parameters with the same name, but under different levels of hierarchy. local tells the simulator that a parameter name in a subcircuit overrides the same parameter name in a higher level of the hierarchy. global tells the simulator that a parameter name at a higher level of the hierarchy overrides the same parameter name at a lower level.
scale = value	Scaling factor used to scale the parameters in the element card. Default value is 1.
scalm = value	Model scaling factor used to scale the model parameters defined in model cards. Default value is 1.
search = path	Specifies the search path for libraries and included files.
wl = (0|1)	wl changes the order of specified MOS elements from the default order length-width to width-length. Default value is 0.

.param

.param param1=value1 [param2 = val2 ... paramn = valn]

or

.param func_name='expression'

Description

This statement defines parameters and user-defined functions.

Examples

.param vcc=2.5

.param half_vcc='0.5*vcc'

.param g(x)='5*x+0.5'

.param f(x)='g(x)+5*x+0.5'

.subckt or .macro

.subckt subckt_name [port1 ... portn] [par1 = val1 ... parn = valn]

[m = value]

or

.macro subckt_name [port1 ... portn] [par1 = val1 ... parn = valn] [m = value]

Description

These statements specify the beginning of a subcircuit definition. The subcircuit can have zero ports when all the nodes used in the subcircuit definition are declared global. A subcircuit definition can contain elements, subcircuit calls, nested subcircuit definitions, as well as simulation output statements (see "Supported SPICE Format Simulation Output Statements" ). Parameters can be declared within subcircuit definitions, on a .subckt or .macro command, or on a subcircuit call. Multipliers are also supported on subcircuits (for example, m = 2).

Example

.subckt inv in out w = wval l = lval

m1 out in vdd vdd pmos w = vval*3 l = lval*2

m2 out in gnd gnd nmos w = wval l = lval

.eom

x1 n1 n2 inv w = 1e-06 l = 2.5e-07

Defines a subcircuit named inv that has two ports and takes two parameters, w and l. It is instantiated by a call named x1, which passes in values for w and l.

.temp

.temp val1 [val2 ... valn]

Description

This statement defines the values of temperature used in the simulations.

Example

.temp 0 50 100

Tells the Virtuoso UltraSim simulator to perform simulations for three temperature values: 0, 50, and 100.

.tran

.tran incr1 stop1 [incr2 stop2 ...incrn stopn] uic [start = value]

+ [sweep var type np start stop]

or

.tran incr1 stop1 [incr2 stop2 ...incrn stopn] uic [start = value]

+ [sweep var start=param_expr1 stop=param_expr2

+ step=param_expr3

or

.tran incr1 stop1 [incr2 stop2 ...incrn stopn] uic [start = value]

[sweep data = dataname]

Description

This statement defines the transient analysis. In a transient analysis, the first calculation is a DC operating point using the DC equivalent model of a circuit. The DC operating point is then used as an initial estimate to solve the next time point in the transient analysis.

If uic is specified, the Virtuoso UltraSim simulator sets the node voltages as defined by .ic statements (or by the ic = parameters in various element statements) and sets unspecified nodes to 0 volts instead of solving the quiescent operating point. The DC operating points of unspecified nodes are set to 0 volts. In a SPICE netlist file, specifying uic has the same effect on the simulation as setting usim_opt dc=0.

Examples

In the following example

.tran 1e-12 1e-08 start = 0 sweep vcc lin 5 2.0 3.0

tells the Virtuoso UltraSim simulator to perform a transient analysis from 0 ns to 10 ns in steps of 1 ps. Additionally, vcc is swept linearly for five values from 2.0 to 3.0.

In the next example

.tran 1ns 1us sweep data = allpars

tells the simulator to perform a transient analysis from 0 ns to 1 us in steps of 1 ns. Additionally, the dataset allpars is used for performing the sweep.

In the next example

.tran 1ns 200ns uic

tells the simulator to perform a transient analysis from 0 ns to 200 ns in steps of 1 ns, without calculating the DC operating point when uic is used.

Supported SPICE Format Simulation Output Statements

Listed below are the supported Virtuoso UltraSim SPICE format simulation output statements. The following sections provide a brief description of each statement.

.lprobe and .lprint

.lprobe tran [low = value] [high = value] [name1 = ]ov1 [[name2 = ]ov2] ...

[[namen = ]ovn] [depth = value] [subckt = name] [exclude = pn1]

[exclude = pn2] ... [preserve=none|all|port]

.lprint tran [low = value] [high = value] [name1 = ]ov1 [[name2 = ]ov2] ...

[[namen = ]ovn] [depth = value] [subckt = name] [exclude = pn1]

[exclude = pn2] ... [preserve=none|all|port]

Description

These statements set up logic probes on nodes for the specified output quantity. The results are sent to a waveform output file. These statements can contain hierarchical names and wildcards for nodes or elements, and can be embedded within the scope of a subcircuit (for more information about wildcards, see "Wildcard Rules" ).

The threshold voltages for .lprint/.lprobe can also be set using the vl and vh options. See "Threshold Voltages for Digital Signal Printing and Measurements" for more information.

Note: Output variables can only be simple output variables.

Arguments

 

tran	Defines the analysis type (transient).
ov1, ov2	Specifies the simple output variables and uses v(node_name) format. The name can be hierarchical and contain wildcards (for example, x?1.*.n*).
low = value	Specifies the voltage threshold for the logic 0 (zero) state. The 0 (logic low) state is probed if the node voltage is less than or equal to low. If the node voltage is between low and high, the X state is probed. If not specified, the global parameter value vl is assigned.
high = value	Specifies the voltage threshold for the logic 1 (one) state. The 1 (logic high) state is probed if the node voltage is higher than or equal to high. If the node voltage is between low and high, the X state is probed. If not specified, the global parameter value vh is assigned.
depth = value	Specifies the depth in the circuit hierarchy that a wildcard name applies. If set as one, only the nodes at the current level are applied (default value is infinity).
subckt = name	Specifies the subcircuit this statement applies to. By default, it applies to the top level. If the statement is already in a subcircuit definition, this parameter is ignored. Setting this parameter is equivalent to defining the statement within a subcircuit declaration.
exclude = pn1, pn2	Specifies the output variables to be excluded from the probe. Names can be node or element names, and can contain wildcards.
preserve=none|all|port	Defines the content of nodes probed with wildcard probing. none probes all nodes and ports connected to active devices (default). Nodes connected only to passive elements are not probed. all probes all nodes, including nodes connected to passive elements, and probes all ports. port only probes ports in subcircuits.

Examples

In the following example

.lprobe low = 0.5 high = 4.5 v(n1)

the voltage on node n1 is converted to logic values using the low and high thresholds, and then output to the waveform output file.

In the next example

.lprobe low = 0.5 high = 4.5 v(*) v(BUF.n1) depth = 2 subckt = INV

the logic states are probed for all the nodes within the subcircuit named INV and one level below in the circuit hierarchy. In this case, the reported names of BUF are appended with the circuit call path from the top level to INV. This is equivalent to the situation where the statement `.lprobe tran v(*) depth = 2' is in the subcircuit definition of INV in the netlist file.

In the next example

.lprobe tran v(*) subckt=VCO preserve=all

RC reduction is constrained to preserve all nodes in VCO. Voltage probing is performed for all nodes in VCO, including internal nodes that are only connected to resistors and capacitors.

In the next example

.lprobe tran v(*) exclude=net* exclude=bl*

probes all node voltages except the voltages for nodes matching the pattern net* and bl*. The high and low threshold voltage is set by global parameters vh and vl, respectively.

In the next example

.lprobe low = 0.5 high = 4.5 v(*) exclude=*$*

or

.lprint low = 0.5 high = 4.5 v(*) exclude=*$*

the voltage on all nodes is converted to logic values using the low and high thresholds, and then output to the waveform output file. Nodes containing the $ symbol are excluded.

.malias

.malias model_name=alias_name1 <alias_name2 ...>

Description

The Virtuoso UltraSim simulator supports .malias, an option used to create an alias name for a model. To create an alias, specify the following in the netlist file:

.malias model_name=alias_name1 <alias_name2 ... >

You can use alias_name1 ... the same way as the model_name.

Note: This option is only supported at the top level of the netlist file.

Arguments

 

alias_name	Specifies the alias name used for the model
model_name	Specifies the model name

.measure

.measure tran|tran_cont meas_name trig ... targ ...

Description

This statement defines the measurement that is performed for propagation, delay, rise time, fall time, average voltage, peak-to-peak voltage, and minimum and maximum voltage over a specified period, and over a number of other user-defined variables. The measurement can be used for power analysis on elements or subcircuits (see Examples).

The continuous measurement feature of the Virtuoso UltraSim simulator can be enabled by specifying the tran_cont option in the .measure statement. This type of measure performs the specified measurement continuously until the simulation ends. A measure output file named cont_<meas_name>.mtx is generated and reports the continuous measurement results.

The .measure statement can also be embedded within a subcircuit definition in the netlist file. The measure name is appended with the call path name from the top-level to the instances of the subcircuit. The .measure statement can also be used to perform the measurement of all output variables, including expression probes already defined in the .probe expr() statement.

The Virtuoso UltraSim simulator supports linked measure statements applicable for all the measure functions listed below. Some measure statements can depend on others by having names of other measures in expressions (instead of parameters). These expressions cannot contain node voltages and element currents. To avoid confusion, linked measure statements must be in the same scope (that is, either in the top level or in the same subcircuit definition).

Note: Any signal used in .meas is automatically saved in the waveform file.

The Virtuoso UltraSim simulator supports the following measure functions (descriptions include examples):

Average, RMS, Min, Max, Peak-to-Peak, and Integral

.measure tran meas_name func ov1 [from = value to = value]

Arguments

 

tran	Specifies the transient analysis for the measurement Note: The Virtuoso Ultrasim simulator only supports measurement of transient analysis.
name	User-defined measurement name
ov1	Name of the output variable (it can be the node voltage, branch current of the circuit, or an expression)
func	avg calculates the average area under ov1, divided by the period of time max reports the maximum value of ov1 over the specified interval min reports the minimum value of ov1 over the specified interval pp reports the maximum value, minus the minimum of ov1, over the specified interval rms calculates the square root of the area under the ov1 curve, divided by the period of interest integ reports the integral of ov1 over the specified period
from=	Start time for the measurement period
to=	End time for the measurement period

Examples

The following example

.measure tran avg1 avg v(1) from = 0ns to = 1us

tells the Virtuoso UltraSim simulator to calculate the average voltage of node 1 from 0 ns to 1 us, evaluating the result with variable avg1.

In the next example

.measure tran Q2 integ I(out) from = 0ns to = 1us

tells the simulator to calculate the integral of I(out) from 0 ns to 1us, evaluating the result with variable Q2.

In the next example

.measure tran rms3 rms v(out) from = 0ns to = 1us

tells the simulator to calculate the RMS of the voltage on node out from 0 ns to 1 0ns, evaluating the result with variable rms3.

In the next example

.measure tran rout pp par('v(out)/i(out)')

tells the simulator to calculate the peak-to-peak value of the output resistance at node out, evaluating the result with variable rout.

Current and Power

Description

Used for current and power analysis on elements or subcircuits.

Examples

In the following example

.measure tran current max x0(xtop.x23.out) from=0ns to=1us

the maximum current of port out of instance xtop.x23 is measured from 0 ns to 1 us, excluding all other lower hierarchical subcircuit ports.

In the next example

.measure tran power max `v(xtop.x23.out) * x0(xtop.x23.out)` from=0ns to=1us

the maximum power of port out of instance xtop.x23 is measured 0 ns to 1 us, excluding all other lower hierarchical subcircuit ports.

In the next example

.measure tran current max x(xtop.x23.out) from=0ns to=1us

the maximum current of port out of instance xtop.x23 and all instances below is measured.

In the next example

.measure tran power max `v(xtop.x23.out) * x(xtop.x23.out)` from=0ns to=1us

the maximum power of port out of instance xtop.x23 and all instances below is measured.

In the next example

.measure tran power_avg avg `v(1) * i1(r1)` from=0ns to=1us

the average power on element r1, from 0 ns to 1 us, is measured in the circuit.

In the next example

.measure tran energy integ ` v(xtop.x23.out) * x(xtop.x23.out)` from=0ns to=10us

the integral power (total energy) of port out of instance xtop.x23 and all instances below is measured.

Find and When

.measure tran meas_name find ov1 at = value

or

.measure tran|tran_cont meas_name find ov1 when ov2 = value [td = value]

[rise = r|last] [fall = f|last] [cross = c|last] [from = value to = value]

or

.measure tran|tran_cont meas_name when ov1 = value|ov3 [td = value] [rise = r|last]

[fall = f|last] [cross = c|last] [from = value to = value]

or

.measure tran|tran_cont meas_name when ov1 = ov2 [td = value] [rise = r|last] [fall = f|last] [cross = c|last] [from = value to = value]

Note: The from/to pair, at, and td arguments cannot be specified together with the same .measure statement.

Arguments

 

tran	Specifies the transient analysis for the measurement. Note: The Virtuoso Ultrasim simulator only supports measurement of transient analysis.
meas_name	User-defined measurement name.
when|find	Specifies the when and find functions.
ov1, ov2, ov3	Name of the output variable (it can be the node voltage, branch current of the circuit, or an expression).
td	Time at which measurement starts.
rise=r	Number of rising edges the target signal achieves r times (the measurement is executed).
fall=f	Number of falling edges the target signal achieves f times (the measurement is executed).
cross=c	Total number of rising and falling edges the target signal achieves c times (the measurement is executed). Crossing can be rise or fall.
last	Last cross, fall, or rise event (measurement is executed the last time the find or when condition is true). Note: last is a reserved keyword and cannot be used as a parameter name in .measure statements.
from=	Start time for the measurement period.
to=	End time for the measurement period.

Examples

.measure tran find1 find v(1) at = 0ns

.measure tran find2 find v(1) when v(2) = 2.5 rise = 1

.measure tran when1 v(1) = 2.5 cross = 1

.measure tran when2 v(1) = v(2) cross = 1

.measure tran_cont cont_find3 find v(1) when v(2) = 2.5 rise = 1

.measure tran_cont cont_when3 v(1) = 2.5 cross = 1

.measure tran_cont cont_when4 v(1) = v(2) cross = 1

Parameter

.measure tran meas_name param = 'expr'

Description

This format is specified together with other measures. `expr' can contain the names of other measures, but cannot contain node voltages or element currents.

Note: Since `expr' is a function of previous measurement results, it cannot be a function of node voltage or branch current.

Examples

In the following example

.measure tran avg1 avg v(1) from = 0ns to = 1us

.measure tran avg2 avg v(1) from = 2ns to = 3us

.measure tran avg12 param = 'avg1+avg2'

the measure avg12 returns the sum of the values from avg1 and avg2.

In the next example

.measure tran avg01 avg v(in) from = 0 to = 1e-08

.measure tran time1 when v(1) = 2.5 cross = 1

.measure tran delay1 trig at = 'time1' targ v(t4) val = '0.5*(avg01+0.0112)'
rise = 1

the measure delay1 is calculated based on the results of time1 and avg.

Rise, Fall, and Delay

. measure tran meas_name trig … targ …

Target

targ targ_var val = value [td = value] [cross = value | rise = value | fall = value]

Trigger

trig trig_var val = value [td = value] [cross = value] [rise = value] [fall = value]

or

trig at = value

Arguments

 

tran	Specifies the transient analysis for the measurement. Note: The Virtuoso Ultrasim simulator only supports measurement of transient analysis.
meas_name	User-defined measurement name.
trig	Specifies the beginning of trigger specifications.
targ	Specifies the beginning of target specifications.
trig_var	Name of the output variable that triggers the measurement. If the target is reached before the trigger activates, .measure reports a negative value.
targ_var	Name of the output variable the Virtuoso UltraSim simulator uses to determine the propagation delay with respect to trig_var.
val=value	Value of trig_var or targ_var.
td=value	Time the measurement starts. The simulator counts the number of cross, rise, or fall events that occur after the td value. Default=0.0.
rise=value fall=value cross=value	Number of rise, fall, or cross events the target signal achieves f times (the measurement is executed).
at=value	Special case for trigger specification of measurement start time. The value can be a real time or a measurement result from a previous .measure statement.

Examples

In the first example

.measure tran delay1 trig v(1) val = 0.5 rise = 1 targ v(2) val = 0.5 fall =1

.measure tran_cont delay2 trig v(1) val = 0.5 rise =1 targ v(2) val = 0.5 fall =1

tells the Virtuoso UltraSim simulator to measure the delay from time point v(1), when its value is 0.5 volts on the first rising edge, to time point v(2) when its values is 0.5 volts on the first falling edge.

The second .measure statement continuously reports the delay between v(1) and v(2) until the simulation ends. The additional output file is cont_delay2.mt0.

The next example

.measure tran delay1 trig at=1ns targ v(2) val = 0.5 fall = 1

tells the simulator to measure the delay from 1 ns to time point v(2) when its value is 0.5 volts on the first falling edge.

.probe, .print

.probe [tran] [name1 = ]ov1 [[name2 = ]ov2] ... [[namen = ]ovn]

[depth = value] [subckt = name] net=[name] [exclude = pn1] [exclude = pn2] ...

[preserve=all|port|none]

.print [tran] [name1 = ]ov1 [[name2 = ]ov2] ... [[namen = ]ovn]

[depth = value] [subckt = name] [exclude = pn1] [exclude = pn2] ...

[preserve=all|port|none]

Description

These statements are used to probe nodes and ports or to print simulation results in text and graphic formats. Using any of the specified keywords has the same effect, sending results to a waveform output file. The statements can contain hierarchical names and wildcards for nodes, ports, or elements, and can be embedded within the scope of a subcircuit.

For more information about wildcards, see "Wildcard Rules".

For .print, the Virtuoso UltraSim simulator creates a circuit.print# output file for each simulation run (# starts at 0). The file includes all data for printed variables, with an x in the first column indicating where the .print output data starts, followed by a y indicating where the data ends.

The statements also support the following:

Note: Nonexistent netlist file part names are ignored (warning message with names is printed).

Arguments

 

tran	Defines the analysis type (transient).
ov1, ov2 ...	Name of the output variable (it can be a node voltage, branch current, port current, verilogA instance port voltage, or verilogA instance internal variable value). v(node_name) probes the node_name voltage. The node_name can be hierarchical, and can contain question marks and wildcards. For example: v(x?1.*.n*). i(element_name) prints the branch current output through the element element_name. The element_name can be hierarchical, and can contain question marks and wildcards. For example: i(x?1.*.n*) v1(element_name) probes the voltage of the first terminal for the element element_name, v2 probes the voltage of the second terminal, v3 probes the voltage of the third terminal, and v4 probes the voltage of the fourth terminal (useful when the node name of a terminal is unknown; true for stitched devices). x(instance_port_name) returns the current flowing into the subcircuit port, including all lower hierarchical subcircuit ports. It can be used to probe power and ground ports of an instance, even if the ports are defined as a global node, and do not appear in the subcircuit port list. The instance_port_name can be hierarchical, and can contain question marks and wildcards. For example: x(x?1.*.n*.vdd) x0(instance_port_name) returns the current flowing into the subcircuit port, excluding all other lower hierarchical subcircuit ports. It can be used to probe power and ground ports of an instance, even if the ports are defined as a global node, and do not appear in the subcircuit port list. The instance_port_name can be hierarchical, and can contain question marks and wildcards. For example: x0(x?1.*.n*.vdd). vol = v(node1, node2) probes the voltage difference between node1 and node2, and assigns the result to the variable vol.
	expr = par(`expression') probes the expression of simple output variables and assigns the result to expr. The expression can contain variables in the above two formats, as well as all the mathematical operators, and built-in or user-defined functions. An expression can also contain the names of other expressions. var_name(veriloga_instance) probes the var_name voltage for veriloga_instance. The var_name can be either a port name or an internal variable name of a verilogA module. The veriloga_instance is the instance name of a verilogA module, which can be hierarchical and can contain question marks and wildcards. For example: PD(IO.AN?.B*). all(veriloga_instance) probes all the port voltages and internal variable values for veriloga_instance. The veriloga_instance can be hierarchical and can contain question marks and wildcards. For example: all(IO.AN?.B*).
depth=value	Specifies the depth in the circuit hierarchy that a wildcard name applies to. If it is set as one, only the nodes at the current level are applied (default value is infinity).
subckt=name	Specifies the subcircuit this statement applies to. By default, it applies to the top level. If the statement is already in a subcircuit definition, this parameter is ignored. Setting this parameter is equivalent to defining the statement within a subcircuit declaration. Wildcards are supported.
net=name	Specifies the net name for the pre-layout netlist. When this argument is specified, the software probes the voltage/current of a subnode/parasitic resistor, which is defined in DSPF/SPEF file. Wildcards are supported.
exclude=pn1, pn2	Specifies the output variables to be excluded from the probe. Names can be node or element names, and can contain wildcards.
preserve= none|all|port	Defines the content of nodes probed with wildcard probing. none probes all nodes and ports connected to active devices (default). Nodes connected only to passive elements are not probed. all probes all nodes, including nodes connected to passive elements, and probes all ports. port only probes ports in subcircuits. Note: To apply .preserve=all globally to all .probe statements in a netlist, set the probe_preserve option to all (see probe_preserve Option).

Examples

In the following example

.print v(n1) i1(m1) vdiff = v(n2,n3) expr1 = par(`v(n1)+2*v(n2)')

tells the Virtuoso UltraSim simulator to print the voltage at node n1 and the current i1 for element M1. The voltage difference between nodes n2 and n3 is printed and assigned to vdiff. In addition, an expression of voltages at nodes n1 and n2 is printed and assigned to expr1.

In the next example

.print tran v(*) i(r1) depth = 2 subckt = VCO

tells the simulator to print the voltages for all nodes in the subcircuit named VCO and one level below in the circuit hierarchy. Also printed is the current of the resistor r1 for all the instances of the subcircuit VCO. The reported names of r1 are appended with the circuit call path from the top level to VCO. This is equivalent to the situation where the statement .print tran v(*) i(r1) depth = 2 is written in the subcircuit definition of VCO in the netlist file.

In the next example

.print tran X(xtop1.block1.in) X0(xtop1.block1.in)

tells the simulator to report currents for instance block1, which is instantiated in top level block xtop. X() and returns the current into the subcircuit port in, including all lower hierarchical subcircuit ports. X0() only returns the current into the subcircuit port and excludes all other lower hierarchical subcircuit contributions.

In the next example

.print tran x0(xtop.x23.xinv.out)

tells the simulator to print the current of port out of instance xtop.x23.xinv, excluding all other lower hierarchical subcircuit ports.

Note: To print the subcircuit instance port current, use the format specified in this example.

In the next example

.print tran x(xtop.*)

tells the simulator to print the current of ports for instance xtop and all instances below.

In the next example

.probe tran v(*) subckt=VCO preserve=all

RC reduction is constrained to preserve all nodes in VCO. Voltages are probed for all nodes in VCO, including internal nodes that are only connected to resistors and capacitors.

In the next example

.probe tran v(*) exclude=net* exclude=bl* depth=2

probes all node voltages of the top level and one hierarchy below, except for the voltages of nodes matching the pattern net* and bl*.

In the next example

.probe tran v1(x1.x3.mp1) v2(x3.xp.mp4)

probes the drain of x1.x3.mp1 and gate of x3.xp.mp4.

In the next example

.probe tran out(IO.ANA.VREG) ps3(IO.ANA.VREG) all(IO.ANA.C*)

probes the voltage of port out and the value of the internal variable ps3 for the verilogA instance IO.ANA.VREG, as well as all the port voltages and internal variable values for verilogA instances that match the name IO.ANA.C*.

In the next example

.probe v(X0/XINV1/XN0/M0:GATE@m2) net=x1/x0/xinv1/a

probes the voltage of the finger device's node X0/XINV1/XN0/M0:GATE@m2, which is defined in the DSPF file.

In the next example

.probe i1(R1) net=x1/x0/xinv1/a

probes the current of parasitic resistor R1 on net x1/x0/xinv1/a in a SPEF file.

In the next example

.probe v(*) net=[*]

probes all the voltages of all the subnodes of all nets in DSPF/SPEF file.

.print Control Options

.options co=80|132

This option is used to control printout width. The default value is 80, with up to four variables per line in the printout file. If the number of variables in the .print statement exceeds four, then the first four variables are printed in the same line and the rest are printed on the next line. If co = 132 is set, wide printout format is applied, allowing up to eight variables in a line.

.width out=80|132

Similar to the co option, .width is used to define the printout width of the output file (default is 80). out is the keyword used for printout width.

The print time interval is determined by the .tran statement step time. If the netlist file contains Spectre^® .tran options, then the step and outputstart arguments in the Spectre .tran option statement determine the print time step and the first print time point, respectively.

.option ingold = 0|1|2

The ingold option controls the numerical format of the printout (default value is 0) and is specified with the .option statement. The engineering notation, in contrast to exponential format, provides two to three extra significant digits and aligns data columns to facilitate comparison.

 

ingold=0	Engineering format (default)	1.234K, 123M
ingold=1	G format (fixed and exponential)	1.234e+03, .123
ingold=2	E format (exponential SPICE)	1.234e+03, .123e-1

.option measdgt = x

The measdgt option formats the printed numbers in the .measure output files (such as .meas0 and .mt0). x is used to specify the number of digits displayed to the right of the decimal point. The typical value of x is between 1 and 7 (default is 4). You can use .option measdgt with .option ingold to control the output data format.

Examples

Virtuoso UltraSim simulator format (preferred):

.option co=132

SPICE compatible format:

.width out=132

.option numdgt=x

The numdgt option formats the printed number in the .print, .ic0, and voltage.op output files. The x variable is used to specify the number of significant digits. The typical value of x is between 1 and 7 (default is 5). You can use .option numdgt and .option ingold to control the output data format. Using this option does not affect the accuracy of the simulation.

Examples

.option numdgt=7

Supported SPICE Format Expressions

The Virtuoso UltraSim simulator supports the following SPICE format expressions:

Built-In Functions

The Virtuoso UltraSim simulator supports the following built-in functions for Spectre and SPICE modes.

 

Table 2-2  Built-In Functions 

Form	Function	Class	Description
sin(x)	sine	trig	Returns the sine of x in radians
cos(x)	cosine	trig	Returns the cosine of x in radians
tan(x)	tangent	trig	Returns the tangent of x in radians
asin(x)	arc sine	trig	Returns the inverse sine of x in radians
acos(x)	arc cosine	trig	Returns the inverse cosine of x radians
atan(x)	arc tangent	trig	Returns the inverse tangent of x in radians
sinh(x)	hyperbolic sine	trig	Returns the hyperbolic sine of x in radians
cosh(x)	hyperbolic cosine	trig	Returns the hyperbolic cosine of x in radians
tanh(x)	hyperbolic tangent	trig	Returns the hyperbolic tangent of x in radians
asinh(x)	hyperbolic inverse sine	trig	Returns the hyperbolic inverse sine of x in radians
acosh(x)	hyperbolic inverse cosine	trig	Returns the hyperbolic inverse cosine of x in radians
atanh(x)	hyperbolic inverse tangent	trig	Returns the hyperbolic inverse tangent of x in radians
atan2(x,y))	tangent inverse	trig	Returns the inverse tangent of x/y in radians
hypot(x,y)	hypotenuse	trig	Returns the square root of (x*x + y*y)
ln(x)	natural log	trig	Returns the natural log with base e of x
abs(x)	absolute value	math	Returns the absolute value of x: |x|
sqrt(x)	square root	math	Returns the square root of the absolute value of x: sqrt(-x) = -sqrt(|x|)
pow(x,y)	absolute power	math	Returns the value of x raised to the integer part of y: x(integer part of y)
pwr(x,y)	signed power	math	Returns the absolute value of x, raised to the y power, with the sign of x: (sign of x)|x|y
log(x)	natural logarithm	math	Returns the natural logarithm of the absolute value of x, with the sign of x: (sign of x)log(|x|)
log10(x)	base 10 logarithm	math	Returns the base 10 logarithm of the absolute value of x, with the sign of x: (sign of x)log10(|x|)
exp(x)	exponential	math	Returns e, raised to the power x: ex
db(x)	decibels	math	Returns the base 10 logarithm of the absolute value of x, multiplied by 20, with the sign of x:(sign of x)20log10(|x|)
int(x)	integer	math	Returns the integer portion of x
sgn(x)	return sign	math	Returns -1 if x is less than 0 Returns 0 if x is equal to 0 Returns 1 if x is greater than 0
sign(x,y)	transfer sign	math	Returns the absolute value of x, with the sign of y:(sign of y)|x|
gauss	Gaussian distribution function using relative variation	math	Returns only the nominal value
agauss	Gaussian distribution function using absolute variation	math	Returns only the nominal value
unif	uniform distribution function using relative variation	math	Returns only the nominal value
aunif	uniform distribution function using absolute variation	math	Returns only the nominal value
limit	limit distribution function using absolute variation	math	Returns only the nominal value
min(x,y)	smaller of two args	control	Returns the numeric minimum of x and y
max(x,y)	larger of two args	control	Returns the numeric maximum of x and y
ceil(x)	ceiling	algebraic	Returns the ceiling of x
floor(x)	floor	algebraic	Returns the floor of x
fmod(x,y)	fractional mod	algebraic	Returns the mod of x, y

Constants

The Virtuoso UltraSim simulator supports the following constants.

Note: Constants are only valid in Spectre mode.

 

Table 2-3  Constants 

M_E : 2.7182818284590452354

M_LOG2E : 1.4426950408889634074

M_LOG10E : 0.43429448190325182765

M_LN2 : 0.69314718055994530942

M_LN10 : 2.30258509299404568402

M_PI : 3.14159265358979323846

M_TWO_PI : 6.28318530717958647652

M_PI_2 : 1.57079632679489661923

M_PI_4 : 0.78539816339744830962

M_1_PI : 0.31830988618379067154

M_2_PI : 0.63661977236758134308

M_SQRT2 : 1.41421356237309504880

M_SQRT1_2 : 0.70710678118654752440

M_DEGPERRAD : 57.2957795130823208772

P_Q : 1.6021918e-19

P_C : 2.997924562e+8

P_K : 1.3806226e-23

P_H : 6.6260755e-34

P_EPS0 : 8.85418792394420013968e-12

P_U0 : 0.000001256637061436

P_CELSIUS0 : 273.15

Operators

The Virtuoso UltraSim simulator supports the following operators.

 

Table 2-4  Operators 

Form	Function	Description
+	add	Used for addition
-	subtract	Used for subtraction
/	divide	Used for division
*	multiply	Used for multiplication
**	power	Used for power
%	modulus	Used for modulus
<	less than (relational)	Returns 1 if the left operand is less than the right operand (otherwise returns 0)
>	greater than (relational)	Returns 1 if the left operand is greater than the right operand (otherwise returns 0)
<=	less than or equal (relational)	Returns 1 if the left operand is less than or equal to the right operand (otherwise returns 0)
>=	greater than or equal (relational)	Returns 1 if the left operand is greater than or equal to the right operand (otherwise returns 0)
!=	inequality	Returns 1 if the operands are not equal (otherwise returns 0)
==	equality	Returns 1 if the operands are equal (otherwise returns 0)
&&	logical AND	Returns 1 if neither operand is zero (otherwise returns 0)
||	logical OR	Returns 1 if either or both operands are not zero (returns 0 only if both operands are zero)
&	bitwise AND	Returns signed bitwise AND
|	bitwise OR	Returns signed bitwise OR
cond?expr1:expr2	ternary	If cond is true, evaluates expr1 (if false, evaluates expr2)