Contents

Preface

Licensing in Virtuoso UltraSim Simulator

Virtuoso UltraSim Licenses

License Checkout Order

Suspending and Resuming Licenses

Tracking Token Licenses

Related Documents for Virtuoso UltraSim Simulator

Typographic and Syntax Conventions

1

Introduction to Virtuoso UltraSim Simulator

Virtuoso UltraSim Simulator Features

Related Documents for Extended Analyses

Virtuoso UltraSim Simulator in IC Design Flow

Command Line Format

Running the Virtuoso UltraSim Simulator

Virtuoso UltraSim Simulator Options

Virtuoso UltraSim 64-Bit Software

Virtuoso UltraSim Simulator Configuration File

Setting Virtuoso UltraSim Simulator Options

Virtuoso UltraSim Simulator Input/Output Files

Waveform Name Syntax

Virtuoso UltraSim Return Codes

Error and Warning Messages

UltraSim Workshop

2

Netlist File Formats

Supported Netlist File Formats

Spectre

HSPICE

Mixed Spectre and HSPICE

Structural Verilog

Compressed Netlist File

Supported Spectre Model Features

Spectre

Verilog-A

Supported HSPICE Model Features

Syntax Rules

Unit Prefix Symbols

Supported HSPICE Devices and Elements

Bipolar Junction Transistor

Capacitor

Current-Controlled Current Source (F-Element)

Current-Controlled Voltage Source (H-Element)

Diode

Independent Sources

JFET and MESFET

Lossless Transmission Line (T-Element)

Lossy Transmission Line (W-Element)

MOSFET

Mutual Inductor

Resistor

Self Inductor

Voltage-Controlled Current Sources (G-Elements)

Voltage-Controlled Voltage Source (E-Elements)

Supported HSPICE Sources

dc

exp

pwl

pwlz

pulse

sin

pattern

Supported SPICE Format Simulation and Control Statements

.alter

.connect

.data

.end

.endl

.ends or .eom

.global

.ic

.include

.lib

.nodeset

.op

.options

.param

.subckt or .macro

.temp

.tran

Supported SPICE Format Simulation Output Statements

.lprobe and .lprint

.malias

.measure

.probe, .print

Supported SPICE Format Expressions

Built-In Functions

Constants

Operators

3

Simulation Options

Setting Virtuoso UltraSim Simulator Options in Netlist File

Simulation Modes and Accuracy Settings

Simulation Modes

Supported Representative Models Summary

Accuracy Settings

Recommended Simulation Modes and Accuracy Settings

High-Sensitivity Analog Option

analog

Analog Autodetection

DC Operating Simulation Control Options

Operating Point Calculation Method

DC Operating Point Calculation Exit and Report Options

Integration Method

Simulation Tolerances

Simulation Convergence Options

Save and Restart

Strobing Control Options

Modeling Options

MOSFET Modeling

Analog Representative Model for Generic MOSFET Devices

Diode Modeling

minr

Operating Voltage Range

Treatment of Analog Capacitors

Inductor Shorting

Waveform File Format and Resolution Options

Waveform Format

Updating Waveform Files

Waveform File Size

Waveform File Resolution

Node Name Format Control

Miscellaneous Options

Model Library Specification

Warning Settings

Simulation Start Time Option

Simulation Progress Report Control Options

Model Building Progress Report

Local Options Report

Node Topology Report

Resolving Floating Nodes

Flattening Circuit Hierarchy Option

hier

Device Binning

Element Compaction

Threshold Voltages for Digital Signal Printing and Measurements

Hierarchical Delimiter in Netlist Files

MOSFET Gate Leakage Modeling with Verilog-A

Automatic Detection of Parasitic Bipolar Transistors

Duplicate Subcircuit Handling

Duplicate Port Handling

Duplicate Instance Handling

Bus Signal Notation

Bus Node Mapping for Verilog Netlist File

Structural Verilog Dummy Node Connectivity

skip Option

probe_preserve Option

default_chk_substrate Option

Print File Options

Disabling .print Command

Controlling Text Wrapping of Circuit Check Reports

Limiting the Number of Errors Generated by Design Checking Commands

Limiting the Number of Errors Generated by Power Checking Commands

Limiting the Number or Errors Generated by the Timing Analysis Commands

Modifying the Report Format of Violation Conditions for Design Checking Commands

Changing Resistor, Capacitor, or MOSFET Device Values

.reconnect

UMI or CMI Models for Source Elements

Transistor Subcircuit Definition or verilogA Model Selection

Simulator Options: Default Values

4

Post-Layout Simulation Options

RC Reduction Options

ccut

cgnd

cgndr

rcr_fmax

rcut

rshort

rvshort

postl

Excluding Resistors and Capacitors from RC Reduction

preserve

Stitching Files

capfile

dpf

spf

spef

Parsing Options for Parasitic Files

cmin

cmingnd

cmingndratio

dpfautoscale

dpfscale

dpfskipinst

dpfskipinstfile

dpfskipsubckt

dpfskipsubcktfile

rmax

rmaxlayer

rmin

rminlayer

rvmin

speftriplet

spfaliasterm

spfbusdelim

spfcaponly

spfccreport

spfcrossccap

spfconn

spfdeletepin

spffingerdelim

spfhierdelim

spfinstancesection

spfipin

spfkeepcoupling

spfkeepbackslash

spfnegvalue

spfnetpin

spfparadiodes

spfrcreduction

spfrecover

spfscalec

spfscalecrossc

spfscaler

spfserres

spfserresmod

spfskipncap

spfsplitfinger

spfswapterm

spfxtorintop

spfxtorprefix

Selective RC Backannotation

spfactivenet

spfactivenetfile

spfchlevel

spfcnet

spfcnetfile

spfhlevel

spfnetcmin

spfrcnet

spfrcnetfile

spfskipnet

spfskipnetfile

spfskippwnet

spfskipsignet

Error/Warning Message Control Options for Stitching

spferrorreport

spfmsglimit

Stitching Statistical Reports

Frequently Asked Questions

How can I minimize memory consumption?

How can I reduce the time it takes to run a DC simulation?

5

Voltage Regulator Simulation

Overview of Voltage Regulator Simulation

usim_vr

6

Power Network Solver

Detecting and Analyzing Power Networks

usim_pn

pn_level

pn_max_res

pn

UltraSim Power Network Solver

7

Interactive Simulation Debugging

Overview of Interactive Simulation Debugging

General Commands

alias

exec

exit

help

history

runcmd

Log File Commands

close

flush

open

Analysis Commands

conn

describe

elem_i

exi

exitdc

force

forcev

hier_tree

index

match

meas

name

nextelem

node

nodecon

op

probe

release

restart

run

save

spfname

stop

time

value

vni

8

Virtuoso UltraSim Advanced Analysis

Dynamic Checks

Active Node Checking

Design Checking

Dynamic Power Checking

Node Activity Analysis

Node Glitch Analysis

Power Analysis

Wasted and Capacitive Current Analysis

Power Checking

Timing Analysis

Bisection Timing Optimization

Static Checks

Netlist File Parameter Check

Print Parameters in Subcircuit

Resistor and Capacitor Statistical Checks

Substrate Forward-Bias Check

Static MOS Voltage Check

Static Diode Voltage Check

Static Resistance and Capacitance Voltage Check

Static NMOS and PMOS Bulk Forward-Bias Checks

Detect Conducting NMOSFETs and PMOSFETs

Detect NMOS Connected to VDD

Detect PMOS Connected to GND

Static Maximum Leakage Path Check

Static High Impedance Check

Static RC Delay Path Check

Static ERC Check

Static DC Path Check

info Analysis

Partition and Node Connectivity Analysis

Warning Message Limit Categories

9

Static Power Grid Calculator

Analyzing Parasitic Effects on Power Net Wiring

ultrasim -r

Filtering Routine

10

Virtuoso UltraSim Reliability Simulation

Hot Carrier Injection Models

MOSFET Substrate and Gate Current Model

Hot Carrier Lifetime and Aging Model

DC Lifetime and Aging Model

AC Lifetime and Aging Model

Negative/Positive Bias Temperature Instability Model (NBTI/PBTI)

Aged Model

AgeMOS

Reliability Control Statements

.age

.agemethod

.ageproc

.deltad

.hci_only

.maskdev

.minage

.nbti_only

.pbti_only

Virtuoso UltraSim Simulator Option

deg_mod

Reliability Shared Library

uri_lib

Virtuoso UltraSim Simulator Output File

11

Digital Vector File Format

General Definition

Vector Patterns

radix

io

vname

hier

tunit

chk_ignore

chk_window

enable

period

Signal Characteristics

Timing

idelay

odelay

tdelay

slope

tfall

trise

Voltage Threshold

vih

vil

voh

vol

avoh

avol

vref

vth

Driving Ability

hlz

outz

triz

Tabular Data

Absolute Time Mode

Period Time Mode

Valid Values

Vector Signal States

Input

Output

Digital Vector Waveform to Analog Waveform Conversion

Expected Output and Comparison Result Waveforms for Digital Vector Files

Example of a Digital Vector File

Frequently Asked Questions

Can I replace the bidirectional signal with an input and output vector?

How do I verify the input stimuli?

How do I verify the vector check?

12

Verilog Value Change Dump Stimuli

Processing the Value Change Dump File

VCD Commands

VCD File Format

Definition Commands

$date

$enddefinitions

$scope

$timescale

$upscope

$var

$version

Data Commands

data

time_value

Signal Information File

Signal Information File Format

Signal Matches

.alias

.scope

.in

.out

.bi

.chk_ignore

.chkwindow

Signal Timing

.idelay

.odelay

.tdelay

.tfall

.trise

Voltage Threshold

.vih

.vil

.voh

.vol

Driving Ability

.outz

.triz

Hierarchical Signal Name Mapping

Enhanced VCD Commands

Signal Strength Levels

Value Change Data Syntax

Port Direction and Value Mapping

Enhanced VCD Format Example

Expected Output and Comparison Result Waveforms for Value Change Dump Files

Frequently Asked Questions

Is it necessary to modify the VCD/EVCD file to match the signals?

How can I verify the input stimuli?

How do I verify the output vector check?

Why should I use hierarchical signal name mapping?

What is the difference between CPU and user time?

13

Flash Core Cell Models

Device

Models

14

VST/VAVO/VAEO Interfaces

VST Interface

VAVO/VAEO Interface

Index