12 &nbsp;

produces the same result, telling the Virtuoso UltraSim simulator to set the time scale to 1 ns.

$upscope

$upscope $end

Description

The $upscope command card switches from the current circuit level to an upper circuit level in the design hierarchy.

Example

$upscope $end

Note: This card must be used after the $scope card to switch the scope back to the top scope.

$var

$var [var_type] [size] [identifier] [reference] $end

$var [var_type] [size] [identifier] [reference] [index_range] $end

Description

The $var command defines the bus to be dumped into the data section.

Arguments

var_type

The bus type (the Virtuoso UltraSim simulator ignores this information)

size

Number of bits in this bus specified as a decimal number

identifier

The identifier used in the data section; it can be a or a combination of printable ASCII characters

reference

The name of the bus

index_range

The index range of the bus in the following formats:

[MSI:LSI]

[LSI:MSI]

[index] if the size is 1

Note: MSI, LSI, and index must be an integer

Note: If the size is larger than 1, and the index_range is not specified, the Virtuoso UltraSim simulator assigns an index_range of [size-1:0].

The name of the bit is a combination of the reference and the index.

Examples

$var reg 4 % regA [0:3] $end

the names of the four bits in bus regA are regA[0], regA[1], regA[2], and regA[3]. The netlist file referencing these VCD sources must match these names.

$var reg 1 & b [0] $end

the name of the bit is b[0]. The card defined a bit, not a bus, as a size of 1.

$var reg 1 & c $end

the name of the bit is c.

$version UltraSim B2001.2.10 $end

$var reg 4 % regA $end

the names of the four bits in bus regA are regA[3], regA[2], regA[1], and regA[0]. The netlist file referencing these VCD sources must match the names.

$version

$version version $end

Description

The $version command is used to specify the version of the VCD file created. The Virtuoso UltraSim simulator accepts this command card, but does not process it.

Example

Data Commands

In the VCD data section, a time point that starts with a number (#) sign (for example, #100) indicates the beginning of a new card. This card continues until it reads the line before the next card (cards can have multiple lines). It can also contain data values and a command block. A command block begins with one of the following command keywords, $comment or $time_value, and ends with $end.

data

Description

Data is divided into two types that each have their own format:

Bus data

Bit data

The bus data is for buses defined by $var, with a size greater than one. The bit data applies to the bus defined by $var, with a size equal to one. The bus data format is Bvalue bus_identifier.

Examples

b0101 %

the bus with identifier % (defined by $var) has a binary value of 0101. The bit data format is value bus_identifier.

The valid characters for specifying the value are: 0, 1, x, X, z, and Z. Of these characters, x and X are treated as 0 for the input signal, and do not need a vector check for the output signal. The z and Z characters are treated as floating to high-impedance for the input signal, and do not need a vector check for the output signal.

the one bit bus with identifier & (defined by $var) has a binary value of 1.

time_value

#time_value

Description

Each time value (point) is the beginning of a card in the data section.

Example

#100

Time value is equal to 100 time units (time unit is defined by $timescale).

Signal Information File

Note: The information in this section is applicable to both VCD and EVCD formats.

The signal directions are specified in the signal information file. To input signals, the Virtuoso UltraSim simulator applies stimuli to the simulation. The values of the output signals are used to perform a vector check against the simulation results, and vector errors are generated if mismatches occur. The enable signals are required to control the bi-directional signal behavior as input or output signals. All other signals in the VCD or EVCD file, not specified in the signal information file, are ignored by the simulator (warning messages are issued for these signals, based on the scopes specified in the signal information file).

The time scale of the time related cards in the signal information file are controlled by the $timescale card in the VCD file. For example, if $timescale is set to 1 ns and .tdelay to 2, a delay of (2 * 1ns) occurs.

The signal name in the signal information file can be specified by using the bus name or a wildcard (for more information about wildcards, see "Wildcard Rules" ). The signal name specified in the VCD file is in bus/bit format. Table 12-1 provides examples.

**Table 12-1** **Signal Name in VCD File Corresponds to Signal Information File**
VCD File	Signal Information File
P[0] ... P[15]	P[0:15]
P[0] ... P[15]	P[*]
Q[63:32] Q[31:0]	Q[63:0]

The example in Table 12-2 shows an incorrect naming format.

**Table 12-2** **Incorrect Naming Format in Signal Information File**
VCD File	Signal Information File
A[0:15]	A[0:7] A[8:15]

Note: By default, the Virtuoso UltraSim simulator creates flat mapping between the VCD and analog netlist files (the .hier statement can be used to switch to hierarchical name mapping to precisely match signals).

Signal Information File Format

Comment Line

A comment line begins with asterisk (*) or dollar ($) signs.

Continuous Line

A continuous line is indicated by a plus (+) sign.

The maximum length of a line is 1024 characters. If a card is longer than 1024 characters, you need to use the continuous line for the card.

To process VCD and EVCD formats, the following signal characteristics need to be defined in the signal information file:

Signal Matches

In this section, the following statements define the signal matches between the VCD and analog netlist files, signal directions, and output vector check.

.alias

.alias target_busname alias_name

Description

The .alias statement is used to modify the name of the signal bus in the VCD/EVCD file to match the signal name in the netlist file.

By default, the Virtuoso UltraSim simulator maps the bus delimiter from "*[*]" in VCD file to "*<*>" in the analog netlist. For example, the default setting is as follows:

.alias *[*] *<*>

Note: For more information on using the .alias statement in hierarchical signal name mapping, refer to "Hierarchical Signal Name Mapping".

Examples

The following example

.alias *[*] *[*]

tells the Virtuoso UltraSim simulator to keep square brackets as the bus limiter in an analog netlist. This .alias statement is required because *[*] is mapped to *<*> by default (see Table 12-3 ).

**Table 12-3** **.alias *[*] [*] Names**
Bus Name	Signal Name
a[0:3]	a[0], a[1], a[2], a[3]
vec[3:0]	vec[3], vec[2], vec[1], vec[0]

tells the simulator to change the square brackets to angular brackets (see Table 12-4 ).

.alias sig_*[*] vec_*<*>

**Table 12-4** **.alias sig_*[*] vec_*<*> Names**
Bus Name	Signal Name
sig_1[0:3]	vec_1<0>, vec_1<1>, vec_1<2>, vec_1<3>
sig_bus1[3:0]	vec_bus1<3>, vec_bus1<2>, ve_bus1c<1>, vec_bus1<0>

Note: Each scope name causes the Virtuoso UltraSim simulator to process the signals located in the specified scope, but not the signals located in its parent or child scopes.

.alias sig_* vec_*

tells the simulator to change the prefix of the signal names from sig_ to vec_ (see Table 12-5 ).

**Table 12-5** **.alias sig_* vec_ * Names**
Bus Name	Signal Name
sig_1	vec_1
sig_2	vec_2

.scope

.scope scope_name1 [scope_name2 ... scope_nameN]

Description

The .scope statement specifies the target scope located in the definition section of the VCD file. Only the signals defined in the specified scope are processed. Multiple .scope statements in a signal information file are supported.

Arguments

scope_name

The name of the scope specified in the VCD file by the $scope card.

Example

.scope module1 module2

tells the Virtuoso UltraSim simulator to process the signal located in scope module1 and module2.

.in

.in signal_name1 signal_name2 ... signal_nameN

Description

The .in statement defines the specified bus as the input bus.

Arguments

name

The name of the bus specified in the VCD file

Example

$var reg 4 % b [0:3] $end

$var reg 1 * a $end

$var reg 1 & c [4] $end

$var reg 4 % d [0:3] $end

The name of the bus specified in the VCD file

.in b[0:3] a c[4] d[*]

Defines b[0:3], a, c[4], and d[0:3] as the input signals.

.out

.out signal_name1 signal_name2 ... signal_nameN

Description

The .out statement defines the specified bus as the output bus.

Arguments

name

Example

In the VCD File:

$var reg 4 % b [0:3] $end

$var reg 1 * a $end

$var reg 1 & c [4] $end

$var reg 4 % d [0:3] $end

In the signal information file

.out b[0:3] a c[4] d[*]

Defines b[0:3], a, c[4], and d[0:3] as the output signal.

.bi

.bi `enable_signal_expr' signal_name1 signal_name2 ... signal_nameN

Description

The .bi statement defines the specified bus as the bidirectional bus.

The enable signal can be from a VCD/EVCD or an analog netlist file. When an enable signal is from an analog netlist file, it can also be defined as an output signal for a vector check or only used as an enable signal. If a VCD signal is used as an enable signal, it must be declared an input using the .in statement and located in the VCD file. Different from enable statements in the vector file, the logic voltage threshold of an analog enable signal is defined by the .voh and .vol statements.

Note: The enable signal cannot be defined as a bidirectional signal.

The .alias statement can be used to perform name mapping for the enable signal. In hierarchical signal name mapping (.hier 1), a hierarchical structure for the analog netlist file is supported for the enable signal. A period (.) can be used as the hierarchical delimiter to specify the hierarchical signal, and the hierarchical delimiter can be mapped to other delimiters by the .alias statement.

Bit-wise logic operators are supported in an enable signal expression: & (AND), | (OR), ^ (XOR), and ~ (NOT). Additional operators can be created using a combination of the supported operators. The order of processing for the logic operators is NOT > AND > OR, XOR (OR and XOR are processed at the same time). You can use parentheses () around the operators to change the processing order.

Arguments

`enable_signal_expr'

The expression for the enable signals. The bidirectional bus switches to output mode only when its value is high.

Note: You need to use single quotation marks `' for enable signal expressions.

signal_name

The name of the bus specified in the VCD/EVCD file.

Examples

The following example

$var reg 4 % b [0:3] $end

$var reg 1 & en $end

.bi en b[0:3]

defines b[0:3] as the bidirectional signal, which is controlled by the en signal. When en is high, b[0:3] becomes the output signal.

$var reg 4 * myBi [0:3] $end

$var reg 1 # en $end

bi ~en myBi[0:3]

defines myBi[0:3] as the bidirectional signal, which is controlled by the en signal. The enable signal is appended with a tilde (~) sign, so unlike the first example, the en is now high, myBi[0:3] becomes the input signal, and vice versa.

$var reg 4 * myBi_1 [0:3] $end

$var reg 1 # en $end

.bi `en & (ana_en1 ^ X1.ana_en2)' myBi_1[0:3]

.voh 1.5 ana_en* X1.ana_en*

.vol 0.8 ana_en* X1.ana_en*

defines myBi_1[0:3] as the bidirectional signal, which is controlled by the expression `en & (ana_en1 ^ X1.ana_en2)'. When the value of the expression is high, myBi_1[0:3] becomes the input signal, and vice versa. The .voh and .vol statements define the logic voltage threshold of the two analog enable signals.

.chk_ignore

.chk_ignore start_time end_time [signal_name1 ... signal_nameN]

Description

The .chk_ignore statement specifies a window used to ignore output vector checks for a VCD file. You can provide the signal names in order to apply this statement locally. In addition to hierarchical mapping, the hierarchical structure is also given in the signal names. The start_time and end_time arguments must be specified. To define multiple time windows for ignoring output vector checks, use multiple chk_ignore statements.

Arguments

start_time	Defines the start time for the window used to ignore the output vector checks (use the $timescale card in the VCD file to set the time scale).
end_time	Defines the end time for the window used to ignore the output vector checks. You can use end_time=-1 to ignore the entire transient time (use the $timescale card in the VCD file to set the time scale).

Example

.chk_ignore 0 100 X1.out1 Top.digital.pout[*]

.chk_ignore 300 500 X1.out1 Top.digital.pout[*]

.chk_ignore 0 -1 out[*]

tells the Virtuoso UltraSim simulator to ignore the output vector check for signals X1.out1 and Top.digital.pout[*] in the time windows 0 ns to 100 ns and 300 ns to 500 ns, and to ignore the entire transient time for the signal out[*].

.chkwindow

.chkwindow start_time end_time steady [period=const [first=const] ] [ signal_name1 ... signal_nameN ]

Description

The .chkwindow statement specifies a window for output vector checking. The Virtuoso UltraSim simulator only checks the signal states within this window. The signal states outside the window are ignored. The checks occur at every time point specified in the VCD/EVCD file or as defined by the period and first arguments.

Setting the period argument activates periodic window checking. If period is not defined, the first argument is ignored by the simulator.

Note: To activate periodic window checking, you need to include the "period=" and "first=" keywords.

Arguments

start_time	Defines the window start time at which the window starts at time vec_time-start_time. If the period argument is defined, vec_time is the first time point defined by the first argument, and the vector checks are repeated according to the value of period. If the period argument is not defined, vec_time is the time point defined in the VCD/EVCD file.
end_time	Defines the window end time at which the window ends at time vec_time+end_time.
steady = 0 \| 1	If set to 0, then the vector check passes as long as the signal has reached the desired state once. If set to 1, then the signal remains in the desired state for the entire window period to pass the vector check.
period	Activates periodic window checking and defines its time period.
first	Defines the first check point for periodic window checking (only valid when the period argument is also defined).

Examples

.chkwindow 5 5 0

The .chkwindow statement is set to 0, so the waveform passes the vector check (see Figure 12-1 ).

Figure 12-1 Vector Check with .chkwindow Set to 0

.chkwindow 5 5 1

The .chkwindow is statement set to 1 and the signal remains at that state for the entire window period, in order to pass the vector check (see Figure 12-2 ). If the signal matches Figure 12-1 , the vector check fails.

Figure 12-2 Vector Check with .chkwindow Set to 1

$timescale 100ps $end

.chkwindow 5 5 1 period=100 first=20 p[*] out_*

tells the simulator to activate periodic window checking for signals p[*] and out_*. The vector check points start at 2 ns and repeats every 10 ns.

.chkwindow 5 5 1 first=20 X1.Xana.p[*] X1.Xdigital.Xcore.out_*

tells the simulator to ignore the first argument because a valid period argument has not been specified. The other arguments are used in the simulation.

Signal Timing

The signal timing characteristics (delay, rise and fall time) are defined in this section.

Note: The Virtuoso UltraSim simulator checks whether the values of the .trise and .tfall. statements are reasonable (warning message is issued when the defined value is too small or large).

.idelay

.idelay time_value [signal_name1 ... signal_nameN]

Description

The .idelay statement specifies the delay time for the corresponding input signals. If a bidirectional signal is specified, this only applies to the input stage of the bidirectional signal. The default value is 0.0, if .idelay and .tdelay are not set.

Example

All input signals have a time delay of 5 ns.

.idelay 5

$timescale 100 ps $end

.scope Xtop.XI1

.tdelay 0.1 Xtop.XI1.a* Xtop.XI1.b

The Xtop.XI1.a[0:3] and Xtop.XI1.b input signals have a delay time of 10 ps.

.odelay

.odelay time_value [signal_name1 ... signal_nameN]

Description

The .odelay statement specifies the delay time for the corresponding output signals. If a bidirectional signal is specified, this only applies to the output stage of the bidirectional signal. The default value is 0.0, if .odelay and .tdelay are not set.

Example

All output signals have a time delay of 5 ns.

.odelay 5

.tdelay

.tdelay time_value [signal_name1 ... signal_nameN]

Description

The .tdelay statement specifies the delay time for the corresponding input, output, and bidirectional signals. The default value is 0.0, if .tdelay, .idelay, and .odelay are not specified.

Example

All signals have a time delay of 5 ns.

.tdelay 5

.tfall

.tfall time_value [signal_name1 ... signal_nameN ]

Description

The .tfall statement specifies the fall time of the input signal. If .tfall is not specified, the default value is 0.1 n.

Note: The range of voltage level change for time_value is 0-100%.

Examples

all input signals have a fall time of 0.1 ns.

.tfall 0.1

.tfall 0.1 a[0:3] b

input signals a[0:3] and b have a fall time of 0.1 ns.

.trise

.trise time_value [signal_name1 ... signal_nameN]

Description

The .trise statement specifies the rise time of the input signal. If .trise is not specified, the default value is 0.1 n.

Note: The range of voltage level change for time_value is 0-100%.

Examples

all input signals have a rise time of 0.1 ns.

.trise 0.1

As digital vector format, the voltage threshold for logic low and high can be specified using the following statements to convert the input vectors to stimuli or to perform an output vector check.

.trise 0.1 a[0:3] b

input signals a[0:3] and b have a rise time of 0.1 ns.

Voltage Threshold

.vih

.vih voltage_value [signal_name1 ... signal_nameN]

Description

The .vih statement specifies the logic high voltage of the input signal. If .vih is not specified, the default voltage is 3.3.

Examples

tells the Virtuoso UltraSim simulator all input signals have a logic high voltage of 5.0.

.vih 5.0

.vih 5.0 a[*] b

tells the simulator input signals a[0:3] and b have a logic high voltage of 5.0.

.vil

.vil voltage_value [signal_name1 ... signal_nameN]

Description

The .vil statement specifies the logic low voltage of the input signal. If .vil is not specified, the default voltage is 0.0.

Examples

tells the Virtuoso UltraSim simulator all input signals have a logic low voltage of 1.0.

.vil 1.0

.vil 1.0 a[0:3] b

tells the simulator input signals a[0:3] and b have a logic low voltage of 1.0.

.voh

.voh voltage_value [ signal_name1 ... signal_nameN ]

Description

The .voh statement specifies the logic high voltage of signals defined as outputs and signals from the analog netlist file that are used in the signal information file. If .voh is not specified, the default voltage is 3.3.

Examples

tells the Virtuoso UltraSim simulator all output signals have a logic high voltage of 5.0.

.voh 5.0

.out out[0:3] outA

.voh 5.0 out[*] outA

tells the simulator output signals out[0:3] and outA have a logic high voltage of 5.0.

.vol

.vol voltage_value [signal_name1 ... signal_nameN]

Description

The .vol statement specifies the logic low voltage of signals defined as outputs and signals from the analog netlist file that are used in the signal information file. If .vol is not specified, the default voltage is 0.0.

Examples

tells the Virtuoso UltraSim simulator all output signals have a logic low voltage of 1.0.

.vol 1.0

For input stimuli, the output resistance of VCD/EVCD sources can affect Virtuoso UltraSim simulation results. To specify the driving ability of VCD/EVCD sources, use the following statements:

.out out[0:3] outA

.vol 1.0 out[0:3] outA

tells the simulator output signals out[*] and outA have a logic low voltage of 1.0.

Driving Ability

.outz

.outz resistance [signal_name1 ... signal_nameN]

Description

The .outz statement specifies the output resistance for corresponding input signals. If .outz is not specified, the default value is 0.01.

Example

.outz 1meg

All input signals have an output resistance of 1 Megaohm.

.triz

.triz resistance [signal_name1 ... signal_nameN]

Description

The .triz statement specifies the output impedance when the corresponding input signals are in tri-state. If .triz is not specified, the default value is 1,000 Meg.

Example

.triz 500meg

All input signals have an output impedance of 500 Megaohms.

Hierarchical Signal Name Mapping

Hierarchical signal name mapping can be used to precisely match signals between the VCD and analog netlist files, and is defined by the Virtuoso UltraSim simulator hier statement:

.hier 0 | 1

Description

The .hier statement is used to specify hierarchical names in both the VCD and analog netlist files.

Arguments

hier

If hier=0, the Virtuoso UltraSim simulator creates flat mapping between the VCD and analog netlist files (default). To maintain backward compatibility, the hierarchical delimiter is regarded as part of the signal name.

If hier=1, the simulator applies the hierarchical names to the VCD and analog netlist files. The VCD file stimuli are no longer limited to the top level of the analog netlist file. In the VCD info file, the complete hierarchical structure needs to be added to the .scope statement (the hierarchical signals in the analog netlist file are mapped according to the information provided by the .alias statement).

The key differences between flat and hierarchical mapping include:

To match hierarchical signals in the VCD file, the complete hierarchical structure needs to be specified in the .scope, .alias, and .chkwindow statements, as well as in the signal characteristic statements. For flat mapping, only the signal names are needed.

For hierarchical signal name mapping, the statements to define the port direction of the signal are related to the .scope statement, which includes the .in, .out, and .bi statements. When using flat mapping, the multiple scopes defined by the .scope statement are regarded as set. The Virtuoso UltraSim simulator searches all of the scopes to perform a signal match and outputs an error message when the same signal name is defined in more than one VCD scope.

The hierarchical structure of the analog netlist file is specified by the .alias statement when performing hierarchical mapping.

Enhanced Statements

.scope and .in/.out/.bi

When using the Virtuoso UltraSim simulator to apply hierarchical names to the VCD/EVCD and analog netlist files (.hier 1), the hierarchical structure in the VCD/EVCD file must be clearly defined with the .scope statement. The .in, .out, and .bi statements are used to define the signal name in the specified .scope statement and cannot contain the hierarchical structure. For the .bi statement, the enable signal needs to contain the hierarchical path because the signal may belong to a different scope.

The VCD/EVCD signal info file supports multiple .scope statements. The effective scope of each .scope statement is affected by the other statements, requiring the .in, .out, and .bi statements to be in the correct location.

Examples

In the VCD file:

$scope module top $end

$scope module digital $end

$var reg 1 ! din_1 $end

$var reg 1 " en $end

$scope module drv $end

$var reg 1 ! mid[1] $end

$var reg 1 " inout $end

$upscope $end

In the VCD info file:

* The effective scope is top.digital

.scope top.digital

.in din_1 en

* The scope top.digital is ended by the next .scope statement

.scope top.digital.drv

* The effective scope is changed to top.digital.drv

.out mid[*]

.bi top.digital.en inout

.alias

.alias targ_signame alias_signame

The hierarchical structures that are defined in the .scope statement are used only for the VCD/EVCD file, so the .alias statement is needed to map the signals to the lower circuit levels of the analog netlist file.

Note: If multiple .alias statements define the mapping relationship for a signal, the last .alias statement is used by the simulator, and the other statements are overwritten.

Arguments

targ_signame	Specifies the hierarchical signal names (VCD/EVCD format) that are already defined in the .scope statement and .in/.out/.bi statements. The hierarchical delimiter is represented by a period (.).
alias_signame	Specifies the hierarchical signal names of the analog netlist file. The hier_delimiter option defines the hierarchical delimiter.

Examples

.alias TOP.module1.in1 X1.in1

.scope Top.module1

.in in1

tells the Virtuoso UltraSim simulator to map the TOP.module1.in1 defined in the .scope and .in/.out/.bi statements to the signal in1 of instance X1 in the analog netlist file.

.alias Top.module1.sig_*[*] X1.vec_*<*>

.alias *[*] *<*>

tells the simulator for the Top.module1.sig_[0:15] signals, the second .alias statement overwrites the first .alias statement and maps the signals to X1.vec_<0>, ... X1.vec_<15>. Since only the first .alias statement matches the digital_block.datain[*] signals, they are mapped to digital_block.datain<*> of the analog netlist file.

Analog netlist file:

.usim_opt hier_limiter = %

VCD/EVCD info file:

.alias TOP.module1.sig_[*] X1%Xdrv%vec_<*>

.scope Top.module1

.out sig_*

Note: The hierarchical delimiter for the analog netlist file is percent (%), not period (.).

Hierarchical Signal Names

For hierarchical mapping, the signal names in the .alias and .chkwindow statements, as well as in the signal characteristic statements, must have the hierarchical structure in the VCD file.

Examples

.chkwindow -1 5 1 Top.X1.out*

.vih 1.2 X1.in[*]

.vol 0.2 X1.dout1 Xdig.X2.dout1

.tfall 0.2 Xana.X1.in* Xdig.din*

.outz 100 X1.in[*]

Enhanced VCD Commands

Since the EVCD and VCD formats are similar, only the key EVCD format differences will be discussed in this section:

Signal Strength Levels

Value Change Data Syntax

Port Direction and Value Mapping

Signal Strength Levels

Verilog HDL allows scalar net signal values to have a full range of unknown values, and different levels of strength or combinations of levels of strength. For logic operation, multiple-level logic strength modeling resolves combinations of signals into known or unknown values, allowing the behavior of hardware to be represented with improved accuracy.

EVCD signal strength can be defined by eight values, ranging from 0 (weakest) to 7 (strongest). The most commonly used values are 0 and 6. For example, for logic value 0

<0_strength_component> =6 , <1_strength_component> =0

and for logic value 1

<0_strength_component> =0 , <1_strength_component> =6

Note: Logic strength levels are not defined in VCD files because only four states are supported.

The Virtuoso UltraSim simulator ignores strength information (minimal impact on most CMOS circuit designs). If you want to preserve driver strength during simulation, specify .outz in the signal information file for specific signals with different output resistances.

For more information about logic strength modeling, refer to IEEE Std 1364-2001.

Value Change Data Syntax

The EVCD data command is different from the one used with VCD because the EVCD version can provide strength information and additional signal states.

data

p[port_value] [0_strength_component] [1_strength_component] [identifier_code]

Description

The value change section shows the actual value changes at each simulation time increment. Only variables that change value during a time increment are listed. In the EVCD file, strength information and a larger number of value states with port direction are presented in the value change section. The arguments for the EVCD data command are listed below.

Arguments

p	Key character that indicates a port. Note: There is no space between p and port_value.
port_value	State character which contains information about driving direction and the value of the port. The state characters are described in "Port Direction and Value Mapping" (see tables).
0_strength_component	One of the eight Verilog strength values indicating the strength0 component of the value (the Virtuoso UltraSim simulator ignores this value).
1_strength_component	One of the eight Verilog strength values indicating the strength1 component of the value (the Virtuoso UltraSim simulator ignores this value).
identifier_code	The identifier code for the port, which is defined in the $var construct for the port.

Examples

The following example

pU 0 7 <0

tells the Virtuoso UltraSim simulator the one bit bus with identifier <0 (defined by $var) has a binary value of U, and the strength of 0 component is 0 and the strength of 1 component is 7.