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Introduction to Virtuoso UltraSim Simulator

The Virtuoso^® UltraSim^™ simulator is a fast and multi-purpose single engine, hierarchical simulator, designed to verify analog, mixed signal, memory, and digital circuits. The simulator can be used for functional verification of billion-transistor memory circuits and for high-precision simulation of complex analog circuits. Based on hierarchical simulation technology, the Virtuoso UltraSim simulator is faster and uses less memory than traditional circuit simulators, while maintaining near SPICE accuracy.

The Virtuoso UltraSim simulator supports all major netlist file formats and industry standard device models. It includes a comprehensive post-layout simulation solution and provides powerful deep-submicron analysis capabilities, including timing, power, noise, reliability, and IR drop analysis.

Virtuoso UltraSim Simulator Features

The main features of the Virtuoso UltraSim simulator include:

Along with being the Cadence Fast SPICE transistor level simulator, the Virtuoso UltraSim simulator engine is used with the following Cadence tools:

Related Documents for Extended Analyses

Refer to the following Cadence documentation for more information about these extended analyses:

Virtuoso UltraSim Simulator in IC Design Flow

The Virtuoso UltraSim simulator can be used for pre- and post-layout simulation of analog, mixed signal, memory circuits, and logic designs. Figure 1-1 shows how the simulator fits into the IC design flow.

Figure 1-1  Virtuoso UltraSim Simulator in IC Design Flow

Virtuoso UltraSim pre-layout simulation is used to verify design functionality and timing behavior, analyze the impact of submicron effects on the design, and to optimize the design before starting on the layout. Pre-layout simulation is based on a Spectre or SPICE netlist file, generated by schematic capture or synthesis tools, and also on device model files and input stimuli. An alternative is to input a synthesized or structural Verilog netlist file and the SPICE representation for all logic gates directly into the Virtuoso UltraSim simulator.

Virtuoso UltraSim post-layout simulation is used to verify circuit behavior after the layout design is completed. The simulation considers the effect of slightly changed device sizes, wire delays, and capacitive coupling created during the layout design, and allows the layout designer to optimize the layout design in regard to performance, power consumption, design margins, and robustness and reliability. The Virtuoso UltraSim simulator supports all major post-layout simulation flows, including DSPF/SPEF stitching, DPF backannotation, and the Cadence hierarchical extraction and simulation flow with QRC hierarchical resistor and capacitor extraction (HRCX).

Command Line Format

Running the Virtuoso UltraSim Simulator

The Virtuoso UltraSim simulator can be run from the command line by typing the following statement into a terminal window

ultrasim [-f]<circuit> [Options]

Note: You need to set the path to your_install_dir/bin prior to running the Virtuoso UltraSim simulator.

Virtuoso UltraSim Simulator Options

Table 1-1 lists the Virtuoso UltraSim simulator command line options.

 

Table 1-1  Command Line Options 

Argument	Description
-autoemir [0|1|2]	Specifies whether to run the simulations in the advanced EM/IR flow automatically. In addition, it specifies whether the post-processing of binary data file to generate EM/IR violation maps should be performed automatically through usimEmirUtil. 0: Runs the first simulation only. 1 (Default): Runs both simulations of the advanced EMIR flow. The second simulation is run automatically using the *.emirtap.sp file. 2: Runs the first and second simulation of the advanced EM/IR flow, and performs post-processing through usimEmirUtil. Note: Ensure that the file argument is specified with the .usim_emir statement when you set the value 2 for autoemir.
[-f] circuit	Specifies the circuit netlist filename (the netlist file can be compressed using gzip - see "Compressed Netlist File" for more information)
-h	Prints the designated help message
-info	Prints system information
-64	Runs the 64-bit binary
+config file	Specifies the UltraSim simulator configuration file, which contains the UltraSim simulator options. For example: ultrasim +config usim_opt1.cfg input.scs Where, usim_opt1.cfg is the configuration file.
+optionName value | +optionName=value | +optionName +value
	Specifies a global UltraSim usim_opt option and its value. For example: ultrasim +spfcaponly on test.sp ultrasim +speed=2 test.sp ultrasim +wf_format [psf sst2] test.sp ultrasim +sim_start +10n test.sp
-libpath path	Loads the shared library
-log	Output messages are not copied to a file
+log file	Sends the log output information to the standard output (shell), and the specified file
=log file	Sends the log output information only to the specified file
+lqtimeout value	Specifies a duration (in seconds) for which the software should wait to check-out a license. When you set this option to 0, the Virtuoso UltraSim simulator waits for a license until it is available. Default: 900 seconds Note: +lqt, the abbreviated form of +lqtimeout, can also be used.
+lreport	Reports the number of required tokens in the log file. Note: +lrpt can be used as an abbreviation of +lreport.
-raw rawDir	Specifies the directory in which all parameter storage format (PSF) files are created
-outdir outDir	Specifies the directory in which all of the output files are created
-outname filename	Specifies the base filename which is used when files are created
-format fmt	Displays waveform data in fmt format (possible values for fmt include psf, psfxl, sst2, fsdb, tr0ascii, or wdf; only one entry is allowed)
-uwifmt name	Specifies multiple waveform formats or user-defined output format; use a colon (:) as a delimiter to specify multiple formats
+rtsf	Enables RTSF mode for all PSF files created, and delivers improved viewing performance in the Virtuoso Visualization and Analysis (ViVA) tool
+lsuspend	Turns on license suspend/resume capability. Once the license suspend capability is enabled, you can press Ctrl Z to suspend the licenses and resume them by entering fg in the command line. This feature is beneficial when you are using simulation farms where the licenses being used lower priority jobs might be needed for higher priority jobs. Note: +lsusp, the abbreviated form of +lsuspend, can also be used.
+lorder	Checks licenses in a specific order (use : between license feature names when defining the order)
+multithread=N	Turns on multithreading capability and assigns the simulation jobs to the specified N number of threads. N can be an any integer value between 1 and 16. +mt, the abbreviated form of +multithread, can also be used. Note: There should be no space before and after the assignment operator = when you specify the number of threads. When N is not specified, the UltraSim simulator automatically detects the number of processors and selects the appropriate number of threads to use. By default, the UltraSim simulator does not use multithreading. Important: The multithreading functionality is available only for A, S, and MX simulation modes.
-multithread	Turns off multithreading capability. Note: -mt, the abbreviated form of -multithread, can also be used.
-processor list	Sets the CPU affinity of a process similar to the Linux taskset command. You can specify a numerical list of processors that may contain multiple items, separated by comma. For example: ultrasim -processor 0-3,5,7
-top subckt	Creates a top-level instance of the subcircuit
-V	Displays the Virtuoso UltraSim simulator version This option is case sensitive.
-W	Displays the Virtuoso UltraSim simulator subversion This option is case sensitive.
-I dir	Specifies the search dir directory for .include files
-cmd cmdfile	Command file for interactive simulation debugging
-cmiconfig file	Reads the specified file, which contains compiled-model interface (CMI) configuration commands, to modify the existing CMI configuration
-i	Invokes interactive shell
-spectre	Specifies that the circuit netlist file is in Spectre format
-vlog verilog_file	Specifies that the circuit netlist file is in Verilog format
-r file	Enables the static power grid solver
-rout	Enables the static power grid solver post-layout feature
-ahdllint	Turns on the AHDL linter feature that enables you to detect modeling issues in analog/mixed-signal Hardware Description Languages (AHDL). The AHDL linter feature comprises of static and dynamic lint checks. Static lint checks are performed before analysis. Dynamic lint checks are performed during analysis for dynamic modeling issues. Possible values for -ahdllint are: no, warn, and error. You can enable the AHDL linter feature in UltraSim, as follows: ultrasim -ahdllint netlist.scs For more information on the AHDL linter feature, refer to the Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide.

setenv ULTRASIM_DEFAULTS "optionName1 value optionName2 value ..."

For example, to set the default value of +lqtimeout and +lorder command-line options, use the following setting:

setenv ULTRASIM_DEFAULTS "+lqtimeout 0 +lorder MMSIM"

Notes

Examples

In the following example, the Virtuoso UltraSim simulator writes the information into a log file named circuit.log.

ultrasim circuit.sp =log circuit.log

In the next example, the information is displayed on a standard output display device (same result if -log is not specified in the command).

ultrasim circuit.sp -log

In the next example, the Virtuoso UltraSim simulator writes the information into a log file named circuit.log and also displays it on a standard output display device.

ultrasim circuit.sp +log circuit.log

Waveform Post-Processing Measurement

ultrasim -readraw waveform <options> circuit

Description

The Virtuoso UltraSim simulator supports post-processing measurements based on waveform data from a prior simulation run. To perform measurements on an existing waveform file, add a .measure statement to the original netlist file and rerun the simulation using the -readraw statement (the regular simulation process is skipped). The post-processing measurement results are reported in .pp.mt0 and .pp.meas0 files. The default post-processing log file name is .pp.ulog.

Arguments

 

circuit	The filename of the circuit netlist file that contains the .measure statements. Note: The circuit needs to be the same circuit that generated the waveform being measured.
-readraw waveform	Specifies the name and location of the waveform file. The supported waveform formats are SST2 or FSDB. Note: The location of the waveform file can include the relative or absolute path.
options	The options used for a Virtuoso UltraSim simulation.

The -readraw statement can be used to perform measurements based on signals or expression probes.

Examples

In the following example, the Virtuoso UltraSim simulator saves the v(x1.out) and i(x1.out) signals in the SST2 waveform top.trn file.

ultrasim -spectre top.sp

To perform a power calculation, the following measurement statement is added to the top.sp file.

.measure tran power avg v(x1.out)*i(x1.out) from=0ns to=1us

Note: You can also put .measure statements in a file (for example, measure.txt) and include it in the top.sp file.

To start the post-processing measurement, use the following statement.

ultrasim -readraw top.trn -spectre top.sp

The measurement results are reported in the top.pp.mt0 and top.pp.meas0 files.

Virtuoso UltraSim 64-Bit Software

To run Virtuoso UltraSim 64-bit software,

$your_install_dir/bin/ultrasim -debug3264 -V

You can use the information to verify if the 64-bit version is applicable to your platform, if the 64-bit software is installed, and whether or not it is selected.

$your_install_dir/bin/checkSysConf MMSIM7.0

The script is also available on the Cadence Online Support system.

The list of available executables is located at:

$your_install_dir/bin/64bit

"list" is a list of case-sensitive executable names delimited by a comma (,), semicolon (;), or colon (:).

Note: If CDS_AUTO_64BIT is not set, the 32-bit executable is invoked by default.

Example

setenv CDS_AUTO_64BIT ultrasim
setenv CDS_AUTO_64BIT "exclude:si"

All 64-bit executables are controlled by a wrapper executable. The wrapper invokes the 32-bit or 64-bit executables depending on how the CDS_AUTO_64BIT environment variable is set, or whether the 64-bit executable is installed. The wrapper also adjusts the paths before invoking the 32-bit or 64-bit executables. The wrapper you use to launch the executables is located at your_install_dir/bin.

Note: Do not launch the executables directly from the your_install_dir/bin/64bit or your_install_dir/bin/32bit directory.

Example

$your_install_dir/bin/ultrasim

Virtuoso UltraSim Simulator Configuration File

The Virtuoso UltraSim simulator supports a common configuration file called ultrasim.cfg, enabling you to set the default options for the simulator. This file can be passed into UltraSim with the +config command line option, or it has to be located in one of the following three locations (listed as per search order):

This allows the Virtuoso UltraSim simulator to be configured by you, by the site, or by the project. The Virtuoso UltraSim simulator processes only the first ultrasim.cfg it reads. That is, the ultrasim.cfg in the netlist file directory overwrites the ultrasim.cfg in $HOME and the Virtuoso UltraSim simulator installation directories. The ultrasim.cfg file can contain the following types of commands:

Note: If Spectre syntax is used in the ultrasim.cfg file, simulator lang=spectre needs to be specified at the beginning of the file.

Setting Virtuoso UltraSim Simulator Options

There are multiple ways in which you can specify the UltraSim simulator options. The ways of specifying the options have been listed below in the order of their decreasing priority:

%>ultrasim +speed=2 +rshort=2 +cgnd=1e-16 input.scs

Important: You can only set global options using the above format.

%> ultrasim +config usim_opt1.cfg input.scs

Where, the usim_opt1.cfg file contains the UltraSim simulator options.

For more information on how to set the UltraSim simulator options in the netlist file, see Setting Virtuoso UltraSim Simulator Options in Netlist File.

For more information on where the ultrasim.cfg file can be located and the priority using which the configuration file is processed with respect to its location, see the Virtuoso UltraSim Simulator Configuration File section.

Virtuoso UltraSim Simulator Input/Output Files

The Virtuoso UltraSim simulator recognizes Spectre, SPICE, Verilog-A, and structural Verilog netlist file formats. Figure 1-2 gives an overview of the input and output data required for simulation with the Virtuoso UltraSim simulator. The simulator also supports all major Spectre and SPICE device models (see Chapter 2, "Netlist File Formats," for more details). Digital vector file format and VCD/EVCD stimuli are described in Chapter 11, "Digital Vector File Format" and Chapter 12, "Verilog Value Change Dump Stimuli." The Virtuoso UltraSim simulation options for optimizing simulation accuracy and performance are located in Chapter 3, "Simulation Options."

Figure 1-2  Virtuoso UltraSim Simulator Input/Output Files Diagram

In addition to a log file, the Virtuoso UltraSim simulator creates several output files that contain waveforms, measurements, and analysis results. Each output file has an extension followed by a number. The output files are defined in Table 1-2 below.

 

Table 1-2  Output Files 

Extension	Format	Content
actnode	ASCII	Active node check from acheck (Spectre format)
chk_capacitor	ASCII	Prints capacitor statistics into a log file
chk_resistor	ASCII	Prints resistor statistics into a log file
dcheck	ASCII	Device voltage report from dcheck (Spectre format)
elemcut	ASCII	Contains elements that were cut because their value was less than the specified threshold
fsdb	binary	Fast signal database (FSDB) waveform file (wf_format=fsdb; waveform viewer: nWave)
icmd	ASCII	Interactive mode command history
ilog	ASCII	Interactive mode log file
meas	ASCII	Results from .meas (SPICE format)
mt	ASCII	Results from .meas (SPICE format)
nact	ASCII	Node activity report from usim_nact (Spectre format)
nodecut	ASCII	Cut nodes
pa	ASCII	Element and subcircuit power report from usim_pa (Spectre format)
para_rpt	ASCII	Prints subcircuit parameters into a report file
part_rpt	ASCII	Prints partition and node connectivity analysis results into a report file
pcheck	ASCII	Report for excessive current, DC path leakage current, and high impedance node checks (Spectre format)
pr	ASCII	Partitioning and node connectivity from usim_report (Spectre format)
print	ASCII	Table printout from .print
rpt_chkmosv	ASCII	MOSFET bias voltage check log file
rpt_chkdiov	ASCII	Diode bias voltage check report
rpt_chknmosb	ASCII	NMOSFET drain/source junction check log file
rpt_chknmosvgs	ASCII	MOSFETs with n-type channels check log file
rpt_chkpar	ASCII	Parameter check log file
rpt_chkpmosb	ASCII	PMOSFET drain/source junction check log file
rpt_chkpmosvgs	ASCII	MOSFETs with p-type channels check log file
rpt_chksubs	ASCII	Substrate check log file
rpt_maxleak	ASCII	Maximum DC leakage paths report
rpt_erc	ASCII	Electrical rule check report
rpt_chkrcdelay	ASCII	Static RC delay check report
ta	ASCII	Setup, hold, pulse width, and timing edge violations from usim_ta (Spectre format)
tr0ascii	ASCII	TR0 ASCII format (wf_format=tr0ascii)
tran	binary	Parameter storage format (PSF) waveform file (wf_format=psf; waveform viewers: Virtuoso Visualization and Analysis, and AWD)
trn/dsn	binary	SignalScan Turbo (SST2) waveform file (wf_format=sst2; default format; waveform viewers: SimVision and Virtuoso Visualization and Analysis)
ulog	ASCII	Log file (default if -/=/+log command line option not specified)
vecerr	ASCII	Vector and VCD/EVCD check errors
veclog	ASCII	Vector and VCD/EVCD check results
wdf	binary	WDF waveform file (wf_format=wdf; waveform viewer: Sandworks)

For mt files, the number following the file extension corresponds to the .alter number. For example, if there are two .alter blocks in the netlist file, the mt files are called .mt0, .mt1, and .mt2. The naming convention is HSPICE compatible.

For all other output files, the number corresponds to the number of times the transient analysis was run. For example, if the main netlist file block specifies two different temperatures in the .temp command card, and there is an .alter block that modifies the original .temp command card and specifies new temperature values, then the transient analysis for this netlist file needs to be run three times. All output files generated from the first run would not have a number after the extension. For example, the FSDB file is named circuit.fsdb. The output files generated from the second and third runs are named circuit.fsdb1 and circuit.fsdb2, respectively.

Waveform Name Syntax

The Virtuoso UltraSim simulator generates the waveform output file with the hierarchical signal name (except for PSF format). The signal names have default syntax for SPICE and Spectre netlist file formats.

SPICE Netlist File Syntax

If the input netlist file contains SPICE format, then the generated waveform names use the following syntax:

<output-type>(<node>)

The <output-type> syntax can be either V, I, X0, or any other output type supported by the Virtuoso UltraSim simulator, and <node> is the name of the node specified in the probe statement.

For current probes, the output type (for example, i1 or i2) is based on the branch of the element or node specified in the probe statement.

Spectre Netlist File Syntax

If the input netlist file contains Spectre format, then the generated waveform names use the following syntax:

SPICE and Spectre Netlist File Syntax

If the input netlist file contains SPICE and Spectre syntax, then the default for the waveform name is Spectre syntax. You can override the default behavior of the waveform syntax by using the wf_spectre_syntax option.

For example,

.usim_opt wf_spectre_syntax=1

Setting this option to 1 in the input netlist file forces the output waveform names to follow Spectre syntax, independent of whether the input netlist file is in SPICE, Spectre, or both formats. If the option is set to 0, the output waveform names follow SPICE syntax, independent of the input netlist file format.

Note: The Virtuoso UltraSim simulator waveform output generated in the analog design environment (ADE) is always in Spectre syntax, irrespective of the input netlist file format or the wf_spectre_syntax option.

Virtuoso UltraSim Return Codes

The Virtuoso UltraSim simulator supports two types of return codes: 0 and 1. A return of 0 indicates the simulation was successfully completed and a return of 1 indicates the simulation failed.

Error and Warning Messages

The Virtuoso UltraSim simulator issues error, warning, and information messages when problems are encountered during circuit design simulation.

UltraSim Workshop

The Virtuoso UltraSim simulator tutorials provide examples to help you get started with the simulator. Running the tutorials is recommended to obtain hands-on experience in using the Virtuoso UltraSim simulator features and options. To access the tutorials, see the ultrasim_install_dir/tools/ultrasim/examples directory, which contains the UltraSim Workshop (UltraSim_Workshop.tar.gz file). The workshop provides examples for each UltraSim feature including design checks and EMIR analysis.