While VHDL-AMS is case-insensitive, the DFII 5X library database is case-sensitive. For new cells and new models, use primarily lower case characters for the cell name, entity names, generic names, port names, and architecture names.
Use the ncvhdl -keepcase4use5x option to compel the ncvhdl compiler to retain case sensitivity during compilation. The -use5xkeepcase option keeps the case as for a VHDL cell name in a 5X library.
For example, see the following Mixed_case cell in VHDL code.
entity Mixed_case
...
end entity Mixed_case;
This code creates a Mixed_case cell instead of a mixed_case cell in a 5X library database.
In addition, you can also use the UNIX environment variable CDS_ALT_NMP. When you set it to MATCH as shown below:
setenv CDS_ALT_NMP MATCH
AMS-D in HED and AMS-D in ADE compile using the following command:
ncvhdl -specificunit Abc
instead of
ncvhdl -specificunit \Abc\
If you have a case-sensitive cell name matching the entity name, you should set the UNIX variable CDS_ALT_NMP MATCH variable and use the ncvhdl -keepcase4use5x option.