Analog Instances Inside Generate Statements

The AMS Designer Simulator supports analog instances instantiated inside the generate block hierarchy. The following generate statements are supported.

• generate-for - Also called for-generate, it enables the AMS module items to be instantiated multiple times using a for-loop construct. For example:
  module vs_vams ();
... ... ...
genvar j;
generate
  for (j=0; j<3; j=j+1) begin
  //Analog instance
   beh_vsource V1 (a[i],gnd);
  //SPICE primitive
  resistor #(.r(100k)) R1 (a[j], gnd);
  end
 endgenerate
endmodule

• generate-if - Also called if-generate, it enables the AMS module items to be conditionally instantiated, based on the evaluation of an if-else condition.
  module vs_vams ()
   ... ... ...
  generate
   if ( behModel) begin:behmod
     beh_vsource V1 (in,gnd);
     beh_resistor R1 (in, gnd);
   end
   else begin: spiprim
     vsource #(.dc(5)) V1(in,gnd)
     vsource #(.r(100k)) R1(in,gnd)
   end
  endgenerate
endmodule

• generate-case - Also called case-generate, it enables the module items to be conditionally instantiated, based on a select one-on-many case construct.
  module vs_vams ()
   ... ... ...
  generate
   case: param
    0:
     begin:gen1
     beh_vsource V1 (in,gnd);
     beh_resistor R1 (in, gnd);
    end
    1:
     begin:gen1
      vsource #(.dc(5)) V1 (in,gnd);
      resistor #(.r(100k)) R1 (in,gnd);
    end
   endcase
  endgenerate
endmodule

Currently, the following is not supported:

• Analog behavioral block inside the generate statement

• Declaration of local parameters and nets
• User-defined functions

Related Topics

• Analog Primitives and Subcircuits