Connecting SystemVerilog Interface to DMS/Verilog-AMS (Electrical) Signals

A SystemVerilog (SV) interface may be used to connect modules with mixed-signal content. You must use the -sv_ms command-line option for the SV interface to electrical connections. For instance, for interface signals connecting to VAMS signals such as wreals or for complex interfaces where an interface signal is connecting to DMS reals.

The following are some of the limitations of using SV interface:

There is limited support for coercion when using SystemVerilog interface in mixed-signal designs.

Discipline resolution rules apply as usual, however, not all DR optimizations are supported.

IE optimization, such as back-to-back IE insertion with electrical drivers and receivers is not supported. It is supported for back-to-back scenarios consisting of real type (cds_rnm_pkg types) drivers and real (cds_rnm_pkg type) receivers.

Modports cannot be used with electrical signals.

Ports involving interface signals that are unpacked array wires or user-defined nettypes are not supported.

In designs with complex hierarchy of modules, the -amsoptie option is not supported.

Interface signals that are used in purely digital context remain digital even when connected to electrical signals. This includes the use of signal in clocking blocks.

All limitations for digital implementations for SystemVerilog interface apply to mixed-signal implementations.

The following examples of interface declaration show how a mixed signal net can be declared as a member of an interface.

interface foo; user_nettpe x; modport ...; endinterface

interface foo; wreal1driver x; endinterface

interface foo; wrealsum x; endinterface

interface foo; wrealavg x; endinterface

interface foo; wrealmax x; endinterface

interface foo; wrealmin x; endinterface

interface foo; wreal4state x; endinterface

The following examples highlight how a SystemVerilog interface might be used to connect modules with mixed-signal SystemVerilog DMS objects (including custom nettype and modports)

Use Case 1: When the mixed-signal module instance has an interface port

//Interface Definition(SV)

interface foo;

wreal4state x;

wire x;

endinterface

//bar has an interface port
module bar(foo u);
endmodule

//baz has an interfafce port
module baz(foo u);
endmodule

module tb
foo u()

//explict port connection on instance v of bar
bar v(u)
//implicit (or .*) connection on instance w of baz
baz w(.*)
endmodule

Use Case 2: When the module instance does not have an interface port

//bak does not have an interface port

module bak (inout wreal4state x,
inout wreal4state y);
endmodule

module tb;
foo u();
//explicit port connection on instance v of bar

bar v(u);

//referenced port connection on instance w of bak
bak w(u.x, u.y);
endmodule

The above cases outline the interface connectivity schemes when the modules have real numbered ports. These include wreals and SystemVerilog user-defined nettypes. Such modules are typically written in the SystemVerilog context. When the module is written in the Verilog-AMS context (file with .vams extension), a SystemVerilog wrapper must be used to encapsulate the module before connection with an interface. This is because there is no concept of an interface in the Verilog-AMS language.

Use Case 3: When a module instance is a Verilog-AMS block

`include "disciplines.h"

//bal has an electrical port x and a wreal port y; it is a Verilog-AMS block
module bal(x,y);

electrical x;
wreal y;
end module

//balwrap is a SystemVerilog wrapper for bal
module balwrap(foo,u);
bal v(u.x, u.y);
endmodule

module tb;

// implicit (or .*) connection on instance v or bar
bar v(.*);
//implicit (or .*) connection on instance w of balwrap
balwrap w(.*);
endmodule

Connecting SystemVerilog Interface to DMS/Verilog-AMS (Electrical) Signals

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