Connecting SystemVerilog Multi-Dimensional Array to SPICE/Electrical Ports

To connect SystemVerilog multi-dimensional arrays to SPICE/Electrical ports, use the -sv_ms option. The expressions that connect to SPICE/Electrical at the parent-level/HDL scope can be bit-select, part-select, or a multi-dimensional array bus.

Currently, only the following two-dimensional arrays are supported:

• Packed by unpacked. For example, wire [3:0] clk_out[0:2];
• Packed. For example, wire [3:0][0:2] clk_out;
• Unpacked. For example, wire clk_out[3:0][0:2];

The following scenarios are not currently supported:

• Multi-dimensional arrays to wreal connection
• Multi-dimensional arrays of type reg to an electrical connection
• OOMR multi-dimensional array or a multi-dimensional array in an interface
• Array slice of multi-dimensional arrays to an electrical connection
• Multi-dimensional arrays when used in wildcard connections

Examples

The following example illustrates a bit-selected multi-dimensional array connection. The IE insertion happens at the array, top.clk_out[5][12] and SPICE port, top.x1.p_clk.

//top.sv
module testbench ();
wire [13:10] clk_out[2:7];
pll_top x1(.p_clk(clk_out[5][12]) );
endmodule

//analog.scs
.subckt pll_top p_clk
.ends

The following example illustrates a part-selected multi-dimensional array connection. The IE insertion happens between top.clk_out[5][13] and top.x1.p0_clk_3, top.clk_out[5][12] and top.x1.p0_clk_2, top.clk_out[5][11] and top.x1.p0_clk_1, and top.clk_out[5][10] and top.x1.p0_clk_0.

//top.sv
module testbench ();
wire [14:10] clk_out[2:7];
pll_top x1(.p0_clk(clk_out[5][13:10]) );
endmodule

//analog.scs
.subckt pll_top p0_clk_3 p0_clk_2 p0_clk_1 p0_clk_0
.ends

//generated skeleton:
module pll_top (.p0_clk( { p0_clk_3, p0_clk_2, p0_clk_1,p0_clk_0} ));
…
electrical p0_clk_3;
electrical p0_clk_2;
electrical p0_clk_1;
electrical p0_clk_0;
endmodule

The following example illustrates a multi-dimensional array bus connection. The IE insertion happens between top.clk_out[5][13] and top.x1.p0_clk_3; top.clk_out[5][12] and top.x1.p0_clk_2, top.clk_out[5][11] and top.x1.p0_clk_1, and top.clk_out[5][10] and s.

//top.sv
module testbench ();
wire [13:10] clk_out[2:7];
pll_top x1(.p0_clk(clk_out[5]) );
endmodule

//analog.scs
.subckt pll_top p0_clk_3 p0_clk_2 p0_clk_1 p0_clk_0
.ends 

//generated skeleton:
module pll_top (.p0_clk( { p0_clk_3, p0_clk_2, p0_clk_1,p0_clk_0} ));
…
electrical p0_clk_3;
electrical p0_clk_2;
electrical p0_clk_1;
electrical p0_clk_0;
endmodule

Related Topic

• Features Enabled Using the -sv_ms Option