Creating a Testbench

The major tasks for creating a testbench are as follows:

Create a top level for your design by connecting and instantiating the digital and analog components.
In the following excerpt, wires vcoclk, clock_2, clock_1, clock_0, net036, and p0 connect to the digital instances (counter and divider) and the analog instance (pll_top):

// Testbench`
timescale 1ps/1ps
module testbench ();

...
wire vcoclk, clock_2, clock_1, clock_0, net036, p0;

...
counter counter (reset, vcoclk, clock_2, clock_1, clock_0);
divider divider (vcoclk, net036, p0, reset);
pll_top pll_top (refclk, reset, vcoclk, clock_2, clock_1, clock_0, net036, p0, clk_p0_1x, clk_p0_4x);

endmodule

In a testbench file, you do not have to declare the electrical discipline for any wires even when you use them to connect to the ports of analog instances. You therefore do not need to include the disciplines.vams file.

Create the stimuli to the device under test (DUT).
In the following excerpt, we add reset and refclk:

// Testbench`
timescale 1ps/1ps

module testbench ();
reg reset;reg refclk;
...
wire vcoclk, clock_2, clock_1, clock_0, net036, p0;

initial begin
    reset=1;
    #200 reset=0;
end

initial begin
    refclk=0;
    #200 refclk=1;
end
always #2500 refclk=~refclk;
...
counter counter (reset, vcoclk, clock_2, clock_1, clock_0);
divider divider (vcoclk, net036, p0, reset);
pll_top pll_top (refclk, reset, vcoclk, clock_2, clock_1, clock_0, net036, p0, clk_p0_1x, clk_p0_4x);

endmodule

(Optional) Monitor or self-check the output.
You can monitor the output by adding $monitor to your module definition:initial begin $monitor (y); end

Creating a Testbench

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