Customized Port-Bind Files

A port-bind file contains information about how you want the SPICE subcircuit ports mapped to Verilog buses. You can specify customized bus element mappings as well as port direction. The general format for port bindings is as follows:

SPICEname : VerilogName [ dir=input|output|inout]

where SPICEname and VerilogName are identifiers that do not have to match. Each SPICEname corresponds to a node name or bus in the SPICE subcircuit definition. Each VerilogName corresponds to a wire name or bus in the Verilog module. The port direction specifier is optional.

For scalar nodes, the format is as follows:

node1 : NODE1

For a vector, the format is as follows:

{ myBus_0, myBus_1 } : myBUS[0:1]

You can specify a range of bus elements as follows:

{ busA[0]-busA[10] } : BusA[0:10]

You can specify a customized mapping of elements as follows:

{ busA[10]-busA[5], busA[0]-busA[4] } : busA[0:10]

You can specify a customized mapping of random elements as follows:

{ a_0, a_1, a_2, a_4, b, abc } : bus[0:5]

You might have specified a unary bus delimiter such as & or # :

{ uBus&0, uBus&1, uBus&2, vBus#3, vBus#4, vBus#5 } : bus[0:5]

The following default rules apply to any node or bus that you do not explicitly specify in the port-bind file:

Port names match exactly (name-to-name), including casing

Bus delimiters are [] and <>

These default rules are the same as those that apply when you use autobus.

Customized Port-Bind File Examples

Here is an example that shows how you can use a port-bind file to define port binding between Verilog and SPICE blocks in a very general way. Study the port-bind file format carefully to understand how you can create custom port bindings according to your connection requirements.

You might instantiate subcircuit analog_top in module top as follows:

module top (ext_clk, pll_clk); input ext_clk, pll_clk; wire [0:1] itune; wire res; analog_top xana_top(.in2(pll_clk), .itune(itune), .in1(ext_clk));

... endmodule

Subcircuit analog_top (in analog_top.sp) might look like this:

.subckt analog_to p+ in1 itune[0] itune[1] in2 ... .ends analog_top

Your amsd block might contain the following:

include "analog_top.sp" amsd{ portmap subckt=analog_top file="analog_top.pb" config cell=analog_top use=spice }

If your port-bind file, analog_top.pb , contains the following:

in1 : in2 dir=inout { itune[1], itune[0] } : itune[0:1] dir=inout in2 : in1 dir=inout

the elaborator derives the following information from these port bindings:

Port in1 of SPICE subcircuit analog_top connects to the net in module top that connects to formal port in2 in instance xana_top of analog_top.
The elaborator connects net pll_clk to port in1 of SPICE subcircuit analog_top.
Port itune[1] of SPICE subcircuit analog_top connects to the net in module top that connects to formal port itune[0] in the instance xana_top of analog_top.
The elaborator connects net itune[0] to port itune[1] of SPICE subcircuit analog_top and follows the same logic to connect net itune[1] to port itune[0] of SPICE subcircuit analog_top.
Port in2 of SPICE subcircuit analog_top connects to the net in the module top that connects to formal port in1 in instance xana_top of analog_top.The elaborator connects net ext_clk to port in2 of SPICE subcircuit analog_top.

Here is another example:

// mrcg.v -- Verilog top
module mrcg (ext_clk, pll_clk);
ANALOG_TOP xana_top(.Q_1(Q_1), .Q_2(Q_2), .IN2(pll_clk), .ITUNE(ITUNE), .IN1(ext_clk));
endmodule

// analog_top.cir -- spice leaf
.subckt analog_top q_1 q_2 IN1 itune_0 itune_1 in2
.ends analog_top

// analog_top.pb -- port-bind file
                   q_1 : Q_1          dir=input
                   q_2 : Q_2          dir=input
                   IN1 : in1          dir=inout
{ itune[1], itune[0] } : ITUNE[0:1]   dir=input
                   in2 : IN2          dir=inout

// amsd.scs
include "analog_top.cir"
amsd{
    portmap subckt=analog_top file="analog_top.pb"
    config cell=ANALOG_TOP use=spice
    }

Rules That Apply to Customized Port-Bind Files

Here are some rules to remember when using port-bind files:

The location where the elaborator generates the port-bind files is runDir/portmap_files where runDir is the directory where you run xrun.

If a port-bind file for a certain subcircuit already exists in the default location (mentioned in the previous bullet), the elaborator will not overwrite the file and it will not generate a port-bind file for this case.

The elaborator will never use a port-bind file unless you specify it explicitly in the AMS control file using portmap … file . The software will issue a message that clearly indicates whether the elaborator used a port-bind file.

The port-bind file you specify (using portmap … file ) must have a valid UNIX path, either absolute or relative to the directory where you run xrun.

Any mappings you specify in a port-bind file or in a Verilog module that defines port mappings take precedence over any options you specify explicitly using other options such as autobus , casemap , and busdelim.

Customized Port-Bind Files

Customized Port-Bind File Examples

Rules That Apply to Customized Port-Bind Files

Related Topics